TM4C1231D5PZ_15 Datasheet, PDF (911/1173 Pages) Texas Instruments – Tiva™ TM4C1231D5PZ Microcontroller

Tiva^™ TM4C1231D5PZ Microcontroller
Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x044
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
Type RO
RO
RO
Reset
0
0
0
15
14
13
reserved
Type RO
RO
RO
Reset
0
0
0
RO
RO
RO
0
0
0
12
11
10
9BITIC reserved OEIC
RW
RO
W1C
0
0
0
25
RO
0
9
BEIC
W1C
0
24
23
reserved
RO
RO
0
0
8
PEIC
W1C
0
7
FEIC
W1C
0
22
RO
0
6
RTIC
W1C
0
21
RO
0
5
TXIC
W1C
0
20
19
18
17
16
RO
RO
RO
RO
RO
0
0
0
0
0
4
3
2
1
0
RXIC DSRMIC DCDMIC CTSMIC RIMIC
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
Bit/Field
31:13
12
11
10
9
8
7
Name
reserved
9BITIC
reserved
OEIC
BEIC
PEIC
FEIC
Type
RO
RW
RO
W1C
W1C
W1C
W1C
Reset
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9-Bit Mode Interrupt Clear
Writing a 1 to this bit clears the 9BITRIS bit in the UARTRIS register
and the 9BITMIS bit in the UARTMIS register.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Overrun Error Interrupt Clear
Writing a 1 to this bit clears the OERIS bit in the UARTRIS register and
the OEMIS bit in the UARTMIS register.
Break Error Interrupt Clear
Writing a 1 to this bit clears the BERIS bit in the UARTRIS register and
the BEMIS bit in the UARTMIS register.
Parity Error Interrupt Clear
Writing a 1 to this bit clears the PERIS bit in the UARTRIS register and
the PEMIS bit in the UARTMIS register.
Framing Error Interrupt Clear
Writing a 1 to this bit clears the FERIS bit in the UARTRIS register and
the FEMIS bit in the UARTMIS register.
June 12, 2014
911
Texas Instruments-Production Data