TM4C1231D5PZ_15 Datasheet, PDF (423/1173 Pages) Texas Instruments – Tiva™ TM4C1231D5PZ Microcontroller

Tiva^™ TM4C1231D5PZ Microcontroller
Register 116: Software Reset Control 0 (SRCR0), offset 0x040
This register allows individual modules to be reset. Writes to this register are masked by the bits in
the Device Capabilities 1 (DC1) register.
Important: This register is provided for legacy software support only.
The peripheral-specific Software Reset registers (such as SRWD) should be used to
reset specific peripherals. A write to this legacy register also writes the corresponding
bit in the peripheral-specific register. Any bits that are changed by writing to this legacy
register can be read back correctly with a read of this register. Software must use the
peripheral-specific registers to support modules that are not present in the legacy
registers. If software uses a peripheral-specific register to write a legacy peripheral
(such as Watchdog 1), the write causes proper operation, but the value of that bit is not
reflected in this register. If software uses both legacy and peripheral-specific register
accesses, the peripheral-specific registers must be accessed by read-modify-write
operations that affect only peripherals that are not present in the legacy registers. In
this manner, both the peripheral-specific and legacy registers have coherent information.
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
WDT1
reserved
CAN0
reserved
ADC1 ADC0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
HIB
reserved
WDT0
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:29
28
27:25
24
23:18
Name
reserved
WDT1
reserved
CAN0
reserved
Type
RO
RO
RO
RO
RO
Reset
0
0x0
0
0x0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WDT1 Reset Control
When this bit is set, Watchdog Timer module 1 is reset. All internal data
is lost and the registers are returned to their reset states. This bit must
be manually cleared after being set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CAN0 Reset Control
When this bit is set, CAN module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 12, 2014
423
Texas Instruments-Production Data