SM320F28335GJZMEP Datasheet, PDF (91/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
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GPIOLMPSEL
LPMCR0
SPRS581D – JUNE 2009 – REVISED MAY 2012
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
•
GPIOXINT7SEL
GPIOXNMISEL
Low Power
Modes Block
External Interrupt
PIE
MUX
Asynchronous
path
GPxPUD
Internal
Pullup
GPxQSEL1/2
GPxCTRL
Input
Qualification
GPIOx pin
Asynchronous path
High Impedance
Output Control
0 = Input, 1 = Output
XRS
GPxDAT (read)
00 N/C
01 ^{Peripheral 1 Input}
10 Peripheral 2 Input
11 _{Peripheral 3 Input}
GPxTOGGLE
GPxCLEAR
GPxSET
00
GPxDAT (latch)
01
Peripheral 1 Output
10 Peripheral 2 Output
11 Peripheral 3 Output
00
GPxDIR (latch)
01 Peripheral 1 Output Enable
10 Peripheral 2 Output Enable
11
Peripheral 3 Output Enable
= Default at Reset
GPxMUX1/2
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins.
Figure 4-18. GPIO MUX Block Diagram
Copyright © 2009–2012, Texas Instruments Incorporated
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Peripherals
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