SM320F28335GJZMEP Datasheet, PDF (149/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
www.ti.com
SPRS581D – JUNE 2009 – REVISED MAY 2012
6.15.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax
to Bx). The ADC can start conversions on event triggers from the ePWM, software trigger, or from an
external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected channel on
every Sample/Hold pulse. The conversion time and latency of the Result register update are explained
below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The
selected channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse
width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
Analog Input on
Channel Ax or Bx
Sample n+2
Sample n+1
Sample n
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
ADC Event Trigger from
ePWM or Other Sources
t_d(SH)
t_{dschx_n}
t_{dschx_n+1}
t_SH
Figure 6-34. Sequential Sampling Mode (Single-Channel) Timing
t_d(SH)
t_SH
t_{d(schx_n)}
t_{d(schx_n+1)}
Table 6-52. Sequential Sampling Mode Timing
SAMPLE n SAMPLE n + 1
Delay time from event trigger to
sampling
Sample/Hold width/Acquisition
Width
Delay time for first result to appear
in Result register
Delay time for successive results to
appear in Result register
2.5t_c(ADCCLK)
(1 + Acqps) *
t_c(ADCCLK)
4t_c(ADCCLK)
(2 + Acqps) *
t_c(ADCCLK)
AT 25 MHz
ADC CLOCK,
t_c(ADCCLK) = 40 ns
REMARKS
40 ns with Acqps = 0
160 ns
Acqps value = 0-15
ADCTRL1[8:11]
80 ns
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Electrical Specifications 149