SM320F28335GJZMEP Datasheet, PDF (131/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
www.ti.com
SPRS581D – JUNE 2009 – REVISED MAY 2012
Lead:
LR ≥ t_c(XTIM)
LW ≥ t_c(XTIM)
These requirements result in the following XTIMING register configuration restrictions:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
≥1
≥0
≥0
≥1
≥0
≥0
X2TIMING
0, 1
Examples of valid and invalid timing when not sampling XREADY:
XRDLEAD XRDACTIVE XRDTRAIL
XWRLEAD XWRACTIVE
Invalid ⁽¹⁾
0
0
0
0
0
Valid
1
0
0
1
0
(1) No hardware to detect illegal XTIMING configurations
XWRTRAIL
0
0
X2TIMING
0, 1
0, 1
6.14.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0), then:
1 Lead:
2 Active:
LR ≥ × t_c(XTIM)
LW ≥ t_c(XTIM)
AR ≥ 2 × t_c(XTIM)
AW ≥ 2 × t_c(XTIM)
NOTE
Restriction does not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions :
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
≥1
≥1
≥0
≥1
≥1
≥0
X2TIMING
0, 1
Examples of valid and invalid timing when using synchronous XREADY:
XRDLEAD XRDACTIVE XRDTRAIL
XWRLEAD XWRACTIVE
Invalid ⁽¹⁾
0
0
0
0
0
Invalid ⁽¹⁾
1
0
0
1
0
Valid
1
1
0
1
1
(1) No hardware to detect illegal XTIMING configurations
XWRTRAIL
0
0
0
X2TIMING
0, 1
0, 1
0, 1
6.14.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
If the XREADY signal is sampled in the asynchronous mode (USEREADY = 1, READYMODE = 1), then:
1 Lead:
2 Active:
3 Lead +
Active:
LR ≥ × t_c(XTIM)
LW ≥ t_c(XTIM)
AR ≥ 2 × t_c(XTIM)
AW ≥ 2 × t_c(XTIM)
LR + AR ≥ 4 ×
t_c(XTIM)
LW + AW ≥ 4 ×
t_c(XTIM)
NOTE
Restrictions do not include external hardware wait states.
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Electrical Specifications 131