LM3880_14 Datasheet, PDF (9/20 Pages) Texas Instruments – Power Sequencer

LM3880, LM3880Q
www.ti.com
SNVS451H – AUGUST 2006 – REVISED JULY 2011
If the enable signal remains high for the entire power-up sequence, then the part will operate as shown in the
standard timing diagrams. However, if the enable signal is de-asserted before the power-up sequence is
completed the part will enter a controlled shutdown. This allows the system to walk through a controlled power
cycling, preventing any latch conditions from occuring. This state only occurs if the enable pin is de-asserted
after the completion of timer 1, but before the entire power-up sequence is completed.
When this event occurs, the falling edge of enable pin resets the current timer and will allow the remaining
power-up cycle to complete before beginning the power down sequence. The power down sequence starts
approximately 120ms after the final power-up flag. This allows output voltages in the system to stabilize before
everything is shutdown. An example of this operation can be seen below:
EN
FLAG1
FLAG2
FLAG3
t_d1
t_d2
t_d3
120 ms
t_d4
t_d5
t_d6
Figure 7. Incomplete Sequence
All the internal timers are generated by a master clock that has an extremely low tempco. This allows for tight
accuracy across temperature and a consistent ratio between the individual timers. There is a slight additional
delay of approximately 400 µs to timers 1 and 4 which is a result of the EPROM refresh. This refresh time is in
addition to the programmed delay time and will be almost insignificant to all but the shortest of timer delays.
CUSTOM SEQUENCER
The LM3880 Power Sequencer is based on a CMOS process utilizing an EPROM that has the capability to be
custom programmed at the factory. Approximately 500,000,000 different options are available allowing even the
most complex system to be simply sequenced. Because of the vast options that are possible, customization is
limited to orders of a certain quantity. Please contact National Semiconductor for more information.
The variables that can be programmed include the six delay timers and the reverse sequence order. For the
timers, each can be individually selected from one of the timer selector columns in the table shown below.
However, all six time delays must be from the same column.
Timer Options 1
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
Timer Options 2
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
Timer Options 3
0
6
12
18
24
30
36
42
48
54
60
66
72
78
84
90
Timer Options 4
0
8
16
24
32
40
48
56
64
72
80
88
96
104
112
120
Copyright © 2006–2011, Texas Instruments Incorporated
Product Folder Links: LM3880 LM3880Q
Submit Documentation Feedback
9