DS92CK16_14 Datasheet, PDF (9/17 Pages) Texas Instruments – 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

DS92CK16
www.ti.com
SNAS044C – NOVEMBER 1999 – REVISED APRIL 2013
APPLICATIONS INFORMATION
General application guidelines and hints for BLVDS/LVDS transceivers, drivers and receivers may be found in
the following application notes: LVDS Owner's Manual, AN805(SNOA233), AN807(SNLA027), AN808(SNLA028),
AN903(SNLA034), AN905(SNLA035), AN916(SNLA219), AN971(SNLA165), AN977(SNLA166) .
BLVDS drivers and receivers are intended to be used in a differential backplane configuration. Transceivers or
receivers are connected to the driver through a balanced media such as differential PCB traces. Typically, the
characteristic differential impedance of the media (Zo) is in the range of 50Ω to100Ω. Two termination resistors of
ZoΩ each are placed at the ends of the transmission line backplane. The termination resistor converts the
current sourced by the driver into a voltage that is detected by the receiver. The effects of mid-stream
connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits,
and total termination loading must be taken into account.
The DS92CK16 differential line driver is a balanced current source design. A current mode driver, generally
speaking has a high output impedance (100 ohms) and supplies a constant current for a range of loads (a
voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched
through the load in one direction to produce a logic state and in the other direction to produce the other logic
state. The output current is typically 9.330 mA. The current changes as a function of load resistor. The current
mode requires (as discussed above) that a resistive termination be employed to terminate the signal and to
complete the loop. Unterminated configurations are not allowed. The 9.33 mA loop current will develop a
differential voltage of about 350mV across 37.5Ω (double terminated 75Ω differential transmission backplane)
effective resistance, which the receiver detects with a 280 mV minimum differential noise margin neglecting
resistive line losses (driven signal minus receiver threshold (350 mV – 70 mV = 280 mV)). The signal is centered
around +1.2V (Driver Offset, V_OS) with respect to ground. Note that the steady-state voltage (V_SS) peak-to-peak
swing is twice the differential voltage (V_OD) and is typically 700 mV.
The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its
quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver
increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows
between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed
current between its output without any substantial overlap current. This is similar to some ECL and PECL
devices, but without the heavy static I_CC requirements of the ECL/PECL designs. LVDS requires > 80% less
current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing
RS-422 drivers.
The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when
the transmission of data is not required.
POWER DECOUPLING RECOMMENDATIONS
Bypass capacitors must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1µF
in parallel with 0.01µF, in parallel with 0.001µF at the power supply pin as well as scattered capacitors over the
printed circuit board. Multiple vias should be used to connect the decoupling capacitors to the power planes. A
4.7µF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed
circuit board.
PC BOARD CONSIDERATIONS
Use at least 4 PCB layers (top to bottom); BLVDS signals, ground, power, TTL signals.
Isolate TTL signals from BLVDS signals, otherwise the TTL may couple onto the BLVDS lines. It is best to put
TTL and BLVDS signals on different layers which are isolated by a power/ground plane(s).
Keep drivers and receivers as close to the (BLVDS port side) connectors as possible to create short stub
lengths.
Copyright © 1999–2013, Texas Instruments Incorporated
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