DS92CK16_14 Datasheet, PDF (2/17 Pages) Texas Instruments – 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

DS92CK16
SNAS044C – NOVEMBER 1999 – REVISED APRIL 2013
INPUT
OE
DE
L
L
L
L
H
L
H
L
H
H
Connection Diagram
Table 2. Driver Mode Truth Table
CrdCLK_IN
L
H
L
H
X
CLK/I/O+
L
H
L
H
Z
OUTPUT
CLKI/O−
H
L
H
L
Z
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CLK_OUT
L
H
H
H
H
TSSOP Package
See Package Number PW (R-PDSO-G24)
Pin Name
CLKI/O+
CLKI/O−
OE
Pin #
6
7
2
DE
11
CLK_OUT
CrdCLK_IN
V_CC
13, 15, 17,
19, 21, 23
9
16, 20, 24
GND
V_CCA
1, 12, 14, 18,
22
4
GNDA
NC
5, 8
3, 10
Type
I/O
I/O
I
I
O
TSSOP PACKAGE PIN DESCRIPTIONS
Description
True (Positive) side of the differential clock input.
Complementary (Negative) side of the differential clock input.
OE; this pin is active Low. When High, this pin forces all CLK_OUT pins High. When Low,
CLK_OUT pins logic state is determined by either the CrdCLK_IN or the VID at the CLK/I/O pins
with respect to the logic level at the DE pin. This pin has a weak pullup device to V_CC. If OE
is floating, then all CLK_OUT pins will be High.
DE; this pin is active LOW. When Low, this pin enables the CardCLK_IN signal to the CLKI/O
pins and CLK_OUT pins. When High, the Driver is TRI-STATE, the CLKI/O pins are inputs and
determine the state of the CLK_OUT pins. This pin has a weak pullup device to V_CC. If DE is
floating, then CLKI/O pins are TRI-STATE.
6 Buffered clock (CMOS) outputs.
I
Power
Ground
Input clock from Card (CMOS level or TTL level).
V_CC; Analog V_CCA (Internally separate from V_CC, connect externally or use separate power
supplies). No special power sequencing required. Either V_CCA or V_CC can be applied first, or
simultaneously apply both power supplies.
GND
Power
Ground
Analog V_CCA (Internally separate from V_CC, connect externally or use separate power
supplies). No special power sequencing required. Either V_CCA or V_CC can be applied first, or
simultaneously apply both power supplies.
Analog Ground (Internally separate from Ground must be connected externally).
No Connects
2
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