DS90CF563_13 Datasheet, PDF (9/17 Pages) Texas Instruments – LVDS 18-Bit Color Flat Panel Display (FPD) Link - 65 MHz

www.ti.com
DS90CF563, DS90CF564
SNLS107E – JULY 1997 – REVISED APRIL 2013
SW—Setup and Hold Time (Internal Data Sampling Window)
TCCS—Transmitter Output Skew
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)
Cable Skew—typically 10 ps–40 ps per foot
Figure 16. Receiver LVDS Input Skew Margin
Figure 17. Seven Bits of LVDS in One Clock Cycle
Figure 18. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CF563)
Figure 19. Receiver Powerdown Delay
Copyright © 1997–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: DS90CF563 DS90CF564