DS90CF563_13 Datasheet, PDF (4/17 Pages) Texas Instruments – LVDS 18-Bit Color Flat Panel Display (FPD) Link - 65 MHz

DS90CF563, DS90CF564
SNLS107E – JULY 1997 – REVISED APRIL 2013
Transmitter Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
TCCD
TxCLK IN to TxCLK OUT Delay @ 25°C, V_CC = 5.0V
3.5
(Figure 11)
TCIP
TxCLK IN Period (Figure 9)
15
TCIH
TxCLK IN High Time (Figure 9)
0.35T
TCIL
TxCLK IN Low Time (Figure 9)
0.35T
TSTC
TxIN Setup to TxCLK IN (Figure 9 )
f = 65 MHz
5
THTC
TxIN Hold to TxCLK IN (Figure 9)
2.5
TPDD
Transmitter Powerdown Delay (Figure 20)
TPLLS Transmitter Phase Lock Loop Set (Figure 13)
TPPos0 Transmitter Output Pulse Position 0 (Figure 15)
−0.30
TPPos1 Transmitter Output Pulse Position 1
1.70
TPPos2 Transmitter Output Pulse Position 2
3.60
TPPos3 Transmitter Output Pulse Position 3
5.90
TPPos4 Transmitter Output Pulse Position 4
8.30
TPPos5 Transmitter Output Pulse Position 5
10.40
TPPos6 Transmitter Output Pulse Position 6
12.70
Typ
T
0.5T
0.5T
3.5
1.5
0
1/7 T_clk
2/7 T_clk
3/7 T_clk
4/7 T_clk
5/7 T_clk
6/7 T_clk
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Max
Units
8.5
ns
50
ns
0.65T
ns
0.65T
ns
ns
ns
100
ns
10
ms
0.30
ns
2.50
ns
4.50
ns
6.75
ns
9.00
ns
11.10
ns
13.40
ns
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 6)
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 6)
RCOP
RxCLK OUT Period
RCOH
RxCLK OUT High Time
f = 65 MHz
RCOL
RxCLK OUT Low Time
f = 65 MHz
RSRC
RxOUT Setup to RxCLK OUT
f = 65 MHz
RHRC
RxOUT Hold to RxCLK OUT
f = 65 MHz
RCCD
RxCLK IN to RxCLK OUT Delay @ 25°C, V_CC = 5.0V
(Figure 12)
RPLLS
RSKM
RPDD
Receiver Phase Lock Loop Set (Figure 14)
RxIN Skew Margin ⁽¹⁾ (Figure 16)
Receiver Powerdown (Figure 19)
V_CC = 5V, T_A =25°C
Min Typ Max Units
2.5
4.0
ns
2.0
3.5
ns
15
T
50
ns
7.8
9
ns
3.8
5
ns
2.5 4.2
ns
4.0 5.2
ns
6.4
10.7
ns
10
ms
600
ps
1
μs
(1) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter
output skew (TCCS) and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on
type/length and source clock (TxCLK IN) jitter.
RSKM ≥ cable skew (the, length) + source clock jitter (cycle to cycle)
4
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