DS90CF563_13 Datasheet, PDF (10/17 Pages) Texas Instruments – LVDS 18-Bit Color Flat Panel Display (FPD) Link - 65 MHz

DS90CF563, DS90CF564
SNLS107E – JULY 1997 – REVISED APRIL 2013
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Figure 20. Transmitter Powerdown Delay
Pin Name
TxIN
TxOUT+
TxOUT−
FPSHIFT IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
DS90CF563 Pin Descriptions—FPD Link Transmitter
I/O No.
Description
I 21 TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME, DRDY (also
referred to as HSYNC, VSYNC, Data Enable)
O 3 Positive LVDS differential data output
O 3 Negative LVDS differential data output
I 1 TTL level clock input. The falling edge acts as data strobe
O 1 Positive LVDS differential clock output
O 1 Negative LVDS differential clock output
I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down
I 4 Power supply pins for TTL inputs
I 5 Ground pins for TTL inputs
I 1 Power supply pin for PLL
I 2 Ground pins for PLL
I 1 Power supply pin for LVDS outputs
I 3 Ground pins for LVDS outputs
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
FPSHIFT OUT
PWR DOWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
DS90CF564 Pin Descriptions—FPD Link Receiver
I/O No.
Description
I 3 Positive LVDS differential data inputs
I 3 Negative LVDS differential data inputs
O 21 TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY(also referred to as HSYNC, VSYNC, Data Enable)
I 1 Positive LVDS differential clock input
I 1 Negative LVDS differential clock input
O 1 TTL level clock output. The falling edge acts as data strobe
I 1 TTL level input. Assertion (low input) maintains the receiver outputs in the previous state
I 4 Power supply pins for TTL outputs
I 5 Ground pins for TTL outputs
I 1 Power supply for PLL
I 2 Ground pin for PLL
I 1 Power supply pin for LVDS inputs
I 3 Ground pins for LVDS inputs
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