DS64BR111 Datasheet, PDF (9/39 Pages) Texas Instruments – Ultra Low Power 6.4 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

Symbol
Parameter
Conditions
Min
OUTPUT JITTER SPECIFICATIONS (Note 3)
R_J
Random Jitter
No Media
D_J1
Deterministic Jitter ^{Source Amplitude = 700 mV,}
PRBS15 pattern,
6.4 Gbps
VOD = Default, EQ =
minimum, DE = 0 dB
Equalization
D_JE1
Residual Deterministic 8 meter 30AWG Cable on
Jitter
Input
10.3125 Gbps
Source = 700 mV, PRBS15
pattern
EQ = 0F'h; See Figure 15
D_JE2
Residual Deterministic
30" FR4 on Inputs
Jitter
Source = 800 mV, PRBS15
6.4 Gbps
pattern
EQ = 16'h; See Figure 13
De-emphasis
D_JD1
Residual Deterministic 10” 4 mil stripline FR4 on
Jitter
Outputs
6.4 Gbps
Source = 700 mV, PRBS15
pattern
EQ = 00 (Min), DE = 010'b
See Figure 17
Typ
0.35
0.065
Max
Units
ps (RMS)
UI
0.15
UI
0.10
UI
0.085
UI
Note 2: “Absolute Maximum Ratings” indicate limits beyond which damage
to the device may occur, including inoperability and degradation of device
reliability and/or performance. Functional operation of the device and/or non-
degradation at the Absolute Maximum Ratings or other conditions beyond
those indicated in the Recommended Operating Conditions is not implied.
The Recommended Operating Conditions indicate conditions at which the
device is functional and the device should not be operated beyond such
conditions. Absolute Maximum Numbers are guaranteed for a junction
temperature range of -40°C to +125°C. Models are validated to Maximum
Operating Voltages only.
Note 3: Typical jitter reported is determined by jitter decomposition software
on a DSA8200 Oscilloscope.
Note 4: VOH only applies to the DONE# pin; LOS, SCL, and SDA are open-
drain outputs that have no internal pull-up capability. DONE# is a full
LVCMOS output with pull-up and pull-down capability
Note 5: Force +/- 100 uA on output, measure delta V on the Output and
calculate impedance. Mismatch is the percentage difference of OUTn+ and
OUTn- impedance driving the same logic state.
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