DS64BR111 Datasheet, PDF (26/39 Pages) Texas Instruments – Ultra Low Power 6.4 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

TABLE 1. Table 10: SMBus Register Map
Address ^Register
Name
0x00
Device ID
0x01
Control 1
0x02
Control 2
0x04
Control 3
0x05
CRC 1
Bits
Field
Type Default
7 Reserved
R/W 0x00
6:3 I2C Address [3:0]
R
2 EEPROM reading R
done
1 Reserved
RWS
C
0 Reserved
RWS
C
7:6 Idle Control
R/W 0x00
5:3 Reserved
R/W
2 LOS Select
R/W
1:0 Reserved
7 Reserved
6 Reserved
5 LOS override
R/W
R/W 0x00
4 LOS override value
3 PWDN Inputs
2 PWDN Oscillator
1 Reserved
0 Reserved
7:6 eSATA Mode
R/W 0x00
Enable
5 TX_DIS Override
Enable
4 TX_DIS Value
Channel A
3 TX_DIS Value
Channel B
2 Reserved
1:0 EQ CONTROL
7:0 CRC[7:0]
R/W 0x00
EEPROM
Reg Bit
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Description
set bit to 0
[6:3] SMBus strap observation
1: EEPROM Loading
0: EEPROM Done Loading
set bit to 0
set bit to 0
Control
[7]: Continuous talk ENABLE (Channel A)
[6]: Continuous talk ENABLE (Channel B)
[2]: LOS SEL Channel B
Set bits to 0
LOS Monitor Selection
1: Use LOS from CH B
0: Use LOS from CH A
Set bits to 00'b
Set bit to 0
Set bit to 0
LOS pin override enable (1);
Use Normal Signal Detection (0)
1: Normal Operation
0: Output LOS
1: PWDN
0: Normal Operation
Set bit to 0
[7] Channel A (1)
[6] Channel B (1)
1: Override Use Reg 0x04[4:3]
0: Normal Operation - uses pin
1: TX Disabled
0: TX Enabled
Set bit to 0
[1]: Channel B - EQ Stage 4 ON/OFF
[0]: Channel A - EQ Stage 4 ON/OFF
Slave Mode CRC Bits
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