DS64BR111 Datasheet, PDF (18/39 Pages) Texas Instruments – Ultra Low Power 6.4 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

Master EEPROM Mode in the DS100BR111
Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS100BR111 device. The first 3 bytes of the EEPROM
always contain a header common and necessary to control initialization of all devices connected to the I2C bus. CRC enable flag
to enable/disable CRC checking. There is a MAP bit to flag the presence of an address map that specifies the configuration data
start in the EEPROM. If the MAP bit is not present the configuration data start address is derived from the DS100BR111 address
and the configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the EEPROM.
There are 37 bytes of data size for each DS100BR111 device.
FIGURE 6. Typical EEPROM Data Set
30156715
The CRC-8 calculation is performed on the first 3 bytes of header information plus the 37 bytes of data for the DS64BR111 or 40
bytes in total. The result of this calculation is placed immediately after the DS64BR111 data in the EEPROM which ends with
"5454". The CRC-8 in the DS64BR111 uses a polynomial = x⁸ + x² + x + 1
In SMBus master mode the DS64BR111 reads its initial configuration from an external EEPROM upon power-up. Some of the pins
of the DS64BR111 perform the same functions in SMBus master and SMBus slave mode. Once the DS64BR111 has finished
reading its initial configuration from the external EEPROM in SMBus master mode it reverts to SMBus slave mode and can be
further configured by an external controller over the SMBus. The connection to an external SMBus master is optional and can be
omitted for applications were additional security is desirable. There are two pins that provide unique functions in SMBus master
mode.
• DONE#
• READEN#
When the DS64BR111 is powered up in SMBus master mode, it reads its configuration from the external EEPROM when the
READEN# pin goes low. When the DS64BR111 is finished reading its configuration from the external EEPROM, it drives the
DONE# pin low. In applications where there is more than one DS64BR111 on the same SMBus, bus contention can result if more
than one DS64BR111 tries to take control of the SMBus at the same time. The READEN# and DONE# pins prevent this bus
contention. The system should be designed so that the READEN# pin from one DS64BR111 in the system is driven low on power-
up. This DS64BR111 will take command of the SMBus on power-up and will read its initial configuration from the external EEPROM.
When it is finished reading its configuration, it will drive the DONE# pin low. This pin should be connected to the READEN# pin of
another DS64BR111. When this DS64BR111 senses its READEN# pin driven low, it will take command of the SMBus and read
its initial configuration from the external EEPROM, after which it will set its DONE# pin low. By connecting the DONE# pin of each
DS64BR111 to the READEN# pin of the next DS64BR111, each DS64BR111 can read its initial configuration from the EEPROM
without causing bus contention.
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