DS10CP154A_14 Datasheet, PDF (9/20 Pages) Texas Instruments – DS10CP154A 1.5 Gbps 4x4 LVDS Crosspoint Switch

DS10CP154A
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SNLS306C – AUGUST 2008 – REVISED APRIL 2013
DS10CP154A OPERATION IN THE SMBUS MODE
The DS10CP154A operates as a slave on the System Management Bus (SMBus) when the EN_smb pin is set to
a high (1). Under these conditions, the SCL pin is a clock input while the SDA pin is a serial data input pin.
Device Address
Based on the SMBus 2.0 specification, the DS10CP154A has a 7-bit slave address. The three most significant
bits of the slave address are hard wired inside the DS10CP154A and are “101”. The four least significant bits of
the address are assigned to pins ADDR3-ADDR0 and are set by connecting these pins to GND for a low (0) or to
VCC for a high (1). The complete slave address is shown in the following table:
1
MSB
Table 5. DS10CP154A Slave Address
0
1
ADDR3
ADDR2
ADDR1
ADDR0
LSB
This slave address configuration allows up to sixteen DS10CP154A devices on a single SMBus bus.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SCK is high.
There are three unique states for the SMBus:
START: A HIGH to LOW transition on SDA while SCK is high indicates a message START condition.
STOP: A LOW to HIGH transition on SDA while SCK is high indicates a message STOP condition.
IDLE: If SCK and SDA are both high for a time exceeding tBUF from the last detected STOP condition or if they
are high for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state.
SMBus Transactions
A transaction begins with the host placing the DS10CP154A SMBus into the START condition, then a byte (8
bits) is transferred, MSB first, followed by a ninth ACK bit. ACK bits are ‘0’ to signify an ACK, or ‘1’ to signify
NACK, after this the host holds the SCL line low, and waits for the receiver to raise the SDA line as an
ACKnowledge that the byte has been received.
Writing to a Register
To write a register, the following protocol is used (see SMBus 2.0 specification):
1) The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
5) The Host drives the 8-bit data byte.
6) The Device drives an ACK bit “0”.
7) The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes Idle and communication with other SMBus devices may now
occur.
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