DS10CP154A_14 Datasheet, PDF (11/20 Pages) Texas Instruments – DS10CP154A 1.5 Gbps 4x4 LVDS Crosspoint Switch

DS10CP154A
www.ti.com
SNLS306C – AUGUST 2008 – REVISED APRIL 2013
Table 7. Switch Configuration Register Truth Table
D1
D0
0
0
0
1
1
0
1
1
Input Routed to the OUT0
IN0
IN1
IN2
IN3
The switch configuration logic has a SmartPWDN circuitry which automatically optimizes the device's power
consumption based on the switch configuration (i.e. It places unused I/O blocks and other unused circuitry in the
power down state).
Control Register
The Control register enables SoftPWDN control, individual output power down (PWDNn) control and LOS
Circuitry Enable control via the SMBus. The following table shows the register mapping.
Bit
D[3:0]
Default
1111
PWDNn
Bit Name
D[4]
x
D[5]
x
D[6]
0
n/a
n/a
EN_LOS
D[7]
0
SoftPWDN
Access
R/W
R/W
R/W
R/W
R/W
Description
Writing a [0] to the bit D[n] will power down the output
OUTn when either the PWDN pin OR the Control
Register bit D[7] (SoftPWDN) is set to a high [1].
Undefined.
Undefined.
Writing a [1] to the bit D[6] will enable the LOS circuitry
and receivers on all four inputs. The SmartPWDN
circuitry will not disable any of the inputs nor any
supporting LOS circuitry depending on the switch
configuration.
Writing a [0] to the bit D[7] will place the device into
the power down mode. This pin is ORed together with
the PWDN pin.
PWDN
0
0
1
1
Table 8. DS10CP154A Power Modes Truth Table
SoftPWDN
0
1
0
1
PWDNn
x
x
x
x
DS25CP104 Power Mode
Power Down Mode. In this mode, all
circuitry is shut down except the minimum
required circuitry for the LOS and SMBus
Slave operation. The SMBus circuitry
allows enabling the LOS circuitry and
receivers on all inputs in this mode by
setting the EN_LOS bit to a [1].
Power Up Mode. In this mode, the
SmartPWDN circuitry will automatically
power down any unused I/O and logic
blocks and other supporting circuitry
depending on the switch configuration.
An output will be enabled only when the
SmartPWDN circuitry indicates that that
particular output is needed for the
particular switch configuration and the
respective PWDNn bit has logic high [1].
An input will be enabled when the
SmartPWDN circuitry indicates that that
particular input is needed for the
particular switch configuration or the
EN_LOS bit is set to a [1].
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