DRV120_15 Datasheet, PDF (9/23 Pages) Texas Instruments – Power-Saving Current Controlled Solenoid Driver

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Feature Description (continued)
DRV120
SLVSBG3B – JUNE 2012 – REVISED JULY 2015
Figure 3. PEAK and HOLD Mode Current Settings
Frequency of the internal PWM clock signal, PWM_CLK, that triggers each ON-cycle can be adjusted by external
resistor, R_OSC, connected between OSC and GND. Frequency as a function of resistor value is shown in
Figure 4. Default frequency is used when OSC is connected to GND directly. PWM frequency as a function of
external fixed adjustment resistor value (greater than 66.67 kΩ) is given in Equation 4.
60kHz
f_PWM = _ROSC × 66.67kW;66.67kW < R_OSC < 2MW
(4)
Figure 4. PWM Clock Frequency Setting
Open-drain STATUS output is deactivated if either undervoltage lockout or thermal shutdown blocks have
triggered.
7.4 Device Functional Modes
The DRV120 transitions through three different states. The first is the OFF state, where the EN pin is low and the
PWM output is off. The second is the PEAK state, which begins when the EN pin is pulled high by an external
controller or internal pullup, and ends once t_KEEP has been reached. During this state, the PWM operates in order
to reach the I_PEAK set by the R_PEAK. Finally, once t_KEEP has been reached, the PWM continues to operate, but at
the I_HOLD level. This continues until the EN pin is forced low again and the PWM turns off.
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