DRV120 Datasheet, PDF (9/16 Pages) Texas Instruments – POWER SAVING CURRENT CONTROLLED SOLENOID DRIVER

DRV120
www.ti.com
SLVSBG3A – JUNE 2012 – REVISED AUGUST 2012
Frequency of the internal PWM clock signal, PWM_CLK, that triggers each ON-cycle can be adjusted by external
resistor, R_OSC, connected between OSC and GND. Frequency as a function of resistor value is shown in
Figure 5. Default frequency is used when OSC is connected to GND directly. PWM frequency as a function of
external fixed adjustment resistor value (greater than 66.67 kΩ) is given below.
60kHz
f_PWM = _ROSC × 66.67kW;66.67kW < R_OSC < 2MW
(4)
Figure 5. PWM Clock Frequency Setting
Open-drain STATUS output is deactivated if either under voltage lockout or thermal shutdown blocks have
triggered.
Copyright © 2012, Texas Instruments Incorporated
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