DRV120 Datasheet, PDF (5/16 Pages) Texas Instruments – POWER SAVING CURRENT CONTROLLED SOLENOID DRIVER

DRV120
www.ti.com
SLVSBG3A – JUNE 2012 – REVISED AUGUST 2012
ABSOLUTE MAXIMUM RATINGS⁽¹⁾⁽²⁾
VALUE
UNIT
VIN
Input voltage range
–0.3 to 28
V
Voltage range on EN, STATUS, PEAK, HOLD, OSC, SENSE, RAMP
–0.3 to 7
V
Voltage range on OUT
–0.3 to 28
V
ESD rating
HBM (human body model)
2000
V
CDM (charged device model)
500
T_J
Operating virtual junction temperature range
T_stg
Storage temperature range
–40 to 125
°C
–65 to 150
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
I_OUT
Average solenoid DC current
V_IN
Supply voltage
C_IN
Input capacitor
L
Solenoid inductance
T_A
Operating ambient temperature
MIN
NOM
MAX UNIT
125
mA
6
12
26
V
1
4.7
µF
1
H
-40
105
°C
THERMAL INFORMATION
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
THERMAL METRIC
Junction-to-ambient thermal resistance⁽¹⁾
Junction-to-case (top) thermal resistance⁽²⁾
Junction-to-board thermal resistance⁽³⁾
Junction-to-top characterization parameter⁽⁴⁾
Junction-to-board characterization parameter⁽⁵⁾
Junction-to-case (bottom) thermal resistance⁽⁶⁾
DRV120
PW
8 PINS
183.8
69.2
112.6
10.4
110.9
N/A
DRV120
PW
14 PINS
122.6
51.2
64.3
6.5
63.7
N/A
UNITS
°C/W
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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