DAC8811ICDGKT Datasheet, PDF (9/21 Pages) Texas Instruments – 16-Bit, Serial Input Multiplying Digital-to-Analog Converter

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DAC8811
SLAS411B – NOVEMBER 2004 – REVISED FEBRUARY 2007
THEORY OF OPERATION (continued)
SDI
D15 D14 D13 D12 D11 D10 D9 D8
D1 D0
CLK
CS
t_(CSS)
t_(DS)
t_(DH)
t_(CH)
t_(CL)
t_(CSH)
Figure 19. DAC8811 Timing Diagram
Table 2. Control Logic Truth Table⁽¹⁾
CLK
CS
Serial Shift Register
DAC Register
X
H
No effect
Latched
↑+
L
Shift register data advanced one bit
Latched
X
H
No effect
Latched
X
↑+
Shift register data transferred to DAC register New data loaded from serial register
(1) ↑+ Positive logic transition; X = Don't care
Table 7.1. Serial Input Register Data Format, Data Loaded MSB First
B15
B0
Bit (MSB) B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 (LSB)
Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
APPLICATION INFORMATION
Stability Circuit
For a current-to-voltage design (see Figure 20), the DAC8811 current output (I_OUT) and the connection with the
inverting node of the op amp should be as short as possible and according to correct PCB layout design. For
each code change there is a step function. If the GBP of the op amp is limited and parasitic capacitance is
excessive at the inverting node then gain peaking is possible. Therefore, for circuit stability, a compensation
capacitor C1 (4 pF to 20 pF typ) can be added to the design, as shown in Figure 20.
V_DD
C1
U1
V_DD
R_FB
V_REF
V_REF
I_OUT
−
GND
+
V_OUT
U2
Figure 20. Gain Peaking Prevention Circuit With Compensation Capacitor
Positive Voltage Output Circuit
As Figure 21 illustrates, in order to generate a positive voltage output, a negative reference is input to the
DAC8811. This design is suggested instead of using an inverting amp to invert the output due to tolerance
errors of the resistor. For a negative reference, V_OUT and GND of the reference are level-shifted to a virtual
ground and a -2.5 V input to the DAC8811 with an op amp.
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