BQ29200_16 Datasheet, PDF (9/24 Pages) Texas Instruments – Voltage Protection with Automatic Cell Balance

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bq29200, bq29209
SLUSA52C – SEPTEMBER 2010 – REVISED MARCH 2016
Feature Description (continued)
If the cell overvoltage condition is removed before the external capacitor reaches the reference voltage, the
internal current source is disabled and an internal discharge block is employed to discharge the external
capacitor down to 0 V. In this instance, the OUT pin remains in a low state.
8.3.2 Cell Voltage > V_PROTECT
When one or both of the cell voltages rises above V_PROTECT, the internal comparator is tripped, and the delay
begins to count to t_d. If the input remains above V_PROTECT for the duration of t_d, the bq2920x output changes from
a low to a high state, by means of an internal pull-up network, to a regulated voltage of no more than 9.5 V when
I_OH = 0 mA.
The external delay capacitor should charge up to no more than the internal LDO voltage (approximately 5 V
typically), and will fully discharge in approximately under 100 ms when the overvoltage condition is removed.
V_PROTECT
Cell Voltage
VC2-VC1,
VC1-GND
V_PROTECT
-
V
HYS
t_d
L
H
OUT
Figure 4. Timing for Overvoltage Sensing
8.3.3 Cell Connection Sequence
NOTE
Before connecting the cells, populate the overvoltage delay timing capacitor, C_CD.
The recommended cell connection sequence begins from the bottom of the stack, as follows:
1. GND
2. VC1
3. VC2
While not advised, connecting the cells in a sequence other than that described above does not result in errant
activity on the OUT pin. For example:
1. GND
2. VC2 or VC1
3. Remaining VCx pin
8.3.4 Cell Balance Enable Control
To avoid prematurely discharging the cells, it is recommended to turn off (pull high) the active-low Cell Balance
Enable Control pin at lower State of Charge (SOC) levels.
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