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AMC7891_14 Datasheet, PDF (9/42 Pages) Texas Instruments – Analog Monitor and Control Circuit with 10-Bit, Multi-Channel ADC and Four DACs, Temperature Sensor, and 12 GPIOs
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AMC7891
www.ti.com
SBAS518A – AUGUST 2011 – REVISED DECEMBER 2011
TIMING SPECIFICATIONS(1)(2)
AVDD = 4.75 to 5.5 V, GPIOVDD = 1.8 to 5.5 V, SPIVDD = 1.8 to 5.5 V, AGND = DGND = 0 V, External ADC reference = AVDD,
TA = –40°C to 105°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
fSCLK SCLK frequency
tR
Input rise time
tF
Input fall time
t1
SCLK cycle time
t2
SCLK high time
t3
SCLK low time
t4
Frame start time
t5
SDI setup time
t6
SDI hold time
t7
Frame stop time
t8
CS high time
t9
SDO delay
t10
Wait time
SPIVDD = 5.5 V
SPIVDD = 2.7 V
SPIVDD = 1.8 V
10% to 90% of SPIVDD
10% to 90% of SPIVDD
SPIVDD = 5.5 V
SPIVDD = 2.7 V
SPIVDD = 1.8 V
SPIVDD = 5.5 V
SPIVDD = 2.7 V
SPIVDD = 1.8 V
SPIVDD = 5.5 V
SPIVDD = 2.7 V
SPIVDD = 1.8 V
CS falling edge to SCLK rising edge
SDI valid to falling edge of SCLK
SDI valid after falling edge of SCLK
SCLK falling edge to CS rising edge
SPIVDD = 5.5 V, CL = 10 pF, 1 ns ≤ tR,F(SDO) ≤ 4 ns
SPIVDD = 2.7 V, CL = 10 pF, 1 ns ≤ tR,F(SDO) ≤ 5 ns
SPIVDD = 1.8 V, CL = 10 pF, 2 ns ≤ tR,F(SDO) ≤ 8 ns
CS rising edge to next SCLK rising edge
30 MHz
15 MHz
10 MHz
2 ns
2 ns
33
ns
66
ns
100
ns
13
ns
30
ns
50
ns
13
ns
26
ns
40
ns
5
ns
4
ns
12
ns
15
ns
50
ns
5
16 ns
6
22 ns
8
39 ns
5
ns
(1) Specified by design. Not tested during production.
(2) Digital inputs and outputs timed from a voltage level of SPIVDD/2.
TIMING INFORMATION
t8
t4
CS
SCLK
SDI
t1
tf
t2
t3
tr
Bit 23
t5
t6
t7
t10
Bit 1
Bit 0
Figure 1. Serial Interface Write Timing Diagram
CS
SCLK
SDI
SDO
t8
t4
t7
t1
tf
tr
t2
t3
Read Command
Bit 23
Bit 0
t5
t6
Bit 23
t9
Any Command
Bit 1
Bit 0
Bit 23
Bit 1
Bit 0
Data read from the register selected in previous operation
Figure 2. Serial Interface Read Timing Diagram
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): AMC7891
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