AMC7891_14 Datasheet, PDF (31/42 Pages) Texas Instruments – Analog Monitor and Control Circuit with 10-Bit, Multi-Channel ADC and Four DACs, Temperature Sensor, and 12 GPIOs

AMC7891
www.ti.com
SBAS518A – AUGUST 2011 – REVISED DECEMBER 2011
DAC OUTPUT
The full-scale output range of each DAC is set by the product of the internal reference voltage times a fixed gain
of 2 in the DAC output buffer (2 × V_REF). The full-scale output range of each DAC is limited by the analog power
supply. The maximum and minimum outputs from the DAC cannot exceed AV_DD or be lower than AGND,
respectively.
After power-on or a reset event, the DAC output buffers are in power-down mode. In this mode all dacn_data
registers and DACn data latches are set to their default values, the output buffers are in a high-impedance state
and each DACoutn output pin connects to AGND through an internal 10 kΩ resistor.
DOUBLE-BUFFERED DAC DATA REGISTERS
There are 4 double-buffered DAC data registers. Each DAC has an internal latch preceded by a DAC data
register. Data is initially written to the individual DACn_data register as the value dacn_data[9:0] and then
transferred to its corresponding DACn latch. When the DACn latch is updated, the output from pin DACoutn
changes to the newly set value. When the host reads from DACn_data, the value held in the DACn latch is
returned (not the value held in the data register).
The DACs update mode is determined by the dacn_sync setting in the DAC_sync register. When dacn_sync is
cleared to ‘0’, the DACn is in asynchronous mode. In asynchronous mode, a write to the DACn_data register
results in an immediate update of the DACn latch and corresponding DACoutn output.
Synchronous mode is selected by setting dacn_sync to ‘1’. In synchronous mode writing to the DACn_data
register does not update the DACn latch DACout_n output. Instead, the update occurs only until the dac_load bit
(AMC_config register, bit 11) is set to ‘1’. By setting the DAC_sync register properly, several DACs can be
updated at the same time.
MODE
dacn_sync
Asynchronous
0
Synchronous
1
Table 6. DAC Output Modes
WRITING TO
dac_load
Don’t care
1
OPERATION
Update DACn individually. The DACn latch and DACoutn output are immediately
updated after writing to DACn_data.
Simultaneously update all DACs by internal trigger. Writing ‘1’ to dac_load generates
an internal load DAC trigger signal that updates the DACn latches and DACoutn
outputs with the contents of the corresponding dacn_data[9:0] register values.
The AMC7891 updates the DAC latches only if it has been accessed since the last time dac_load was issued,
thereby eliminating any unnecessary glitch. Any DAC channels that have not been accessed are not reloaded
again. When the DAC latch is updated, the corresponding output changes to the new level immediately.
CLEAR DACS
Each DAC can be cleared using the DAC_clear register. When setting the corresponding dacn_clear bit to ‘1’,
DACn goes to a clear state in which the DACoutn is immediately updated with the predefined value in the
DACn_clear register, regardless of the dacn_sync status. The data register value dacn_data[9:0] does not
change.
When the DAC goes back to normal operation, the DACoutn output is set back to the DACn latch value
regardless of the dac_sync status.
dacn_data
Register Value
dacn_clear
Register Value
DACn
Data Latch
0
1
dacn_clear
DACn
Figure 35. Clear DAC Operation
Copyright © 2011, Texas Instruments Incorporated
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