AMC7891_14 Datasheet, PDF (2/42 Pages) Texas Instruments – Analog Monitor and Control Circuit with 10-Bit, Multi-Channel ADC and Four DACs, Temperature Sensor, and 12 GPIOs

AMC7891
SBAS518A – AUGUST 2011 – REVISED DECEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
RHH PACKAGE
QFN-36
(TOP VIEW)
36 35 34 33 32 31 30 29 28
AV_DD 1
AGND1 2
DGND 3
GPIOV_DD 4
SPIV_DD 5
CS ⁶
SCLK 7
SDI 8
SDO 9
27 GPIOA0
26 GPIOA1
25 GPIOA2
24 GPIOA3
23 GPIOB0
22 GPIOB1
21 GPIOB2
20 GPIOB3
19 DAV
10 11 12 13 14 15 16 17 18
AMC7891 Pin Functions
PIN
I/O
NO.
NAME
DESCRIPTION
1
AV_DD
2 AGND1
I Analog supply voltage. (4.75 V to 5.5 V)
I Analog ground. Ground reference point for all analog circuitry on the device, AGND. Connect AGND1 and
AGND2 to the same potential, AGND.
3 DGND
I Digital ground. Ground reference point for all digital circuitry on the device. Ideally, AGND and DGND should
be at the same potential and must not differ by more than 0.3 V.
4 GPIOV_DD
I GPIO supply voltage. (1.8 V to 5.5 V)
Sets the GPIO operating voltage and threshold levels.
5
SPIV_DD
I Serial interface supply voltage. (1.8 V to 5.5 V)
Sets the serial interface operating voltage and threshold levels.
6 CS
I Active low serial data enable. Schmitt-trigger logic input.
This input is the frame synchronization signal for the serial data. When this signal goes low, it enables the
input shift register and data is sampled on subsequent falling clock edges. The DAC output and register
settings update following the 24th clock. If CS goes high before the 23th clock edge, the command is
ignored.
7 SCLK
I Serial interface clock. Schmitt-trigger logic input.
Maximum SCLK rate is 30MHz.
8 SDI
I Serial interface data input. Schmitt-trigger logic input.
Data is clocked into the input shift register on each falling edge of SCLK.
9 SDO
O Serial interface data output. The SDO pin is in high impedance when CS is high.
Data is clocked out of the input shift register on each rising edge of SCLK.
10 DACOUT3 O DAC3 buffered output. (0 V to AV_DD).
Can source/sink up to 10 mA.
2
Submit Documentation Feedback
Product Folder Link(s): AMC7891
Copyright © 2011, Texas Instruments Incorporated