ADS5400-SP Datasheet, PDF (9/46 Pages) Texas Instruments – 12-Bit, 1-GSPS Analog-to-Digital Converter

ADS5400-SP
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Timing Diagrams
SLAS669C – SEPTEMBER 2010 – REVISED AUGUST 2012
DIFFERENTIAL
ANALOG INPUT
(INP-INN)
N
Aperture
delay
t_a
N+1
N+2
Sample N and RESET pulse
captured here
CLKINP
RESETP
t_RSU
t_RH
t_CLKH
t_CLKL
N
N+1
output output
CLKOUT is reset after 3.5 CLKIN cycles (+ tPD-CLKDIV2 )
tPD-CLKDIV2
Phase 0: CLKOUT in desired
CLKOUTAP state after power up
Phase 1: misaligned by
1 clock after power up
DATA BUS A
tPD-ADATA
Latency of N and SYNCOUTA are matched to 7 CLKIN cycles
N-1
t_su
t_h
N N+1 N+2
SYNCOUTA
(OVRA pins)
If SYNC mode is enabled,
the OVRA pins become SYNCOUTA pins
Sync
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase
will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT
phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of
repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the
CLKOUT phase the same with each RESET event. SYNCOUTA transitions with the same latency as the sample that
is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a
SYNCOUT pulse, which behaves as a data bit. Bus B is not active in single bus mode.
Figure 1. Single Bus Mode
Copyright © 2010–2012, Texas Instruments Incorporated
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