ADS5400-SP Datasheet, PDF (32/46 Pages) Texas Instruments – 12-Bit, 1-GSPS Analog-to-Digital Converter

ADS5400-SP
SLAS669C – SEPTEMBER 2010 – REVISED AUGUST 2012
www.ti.com
The ADS5400 obtains optimum performance when the analog inputs are driven differentially. The circuit in
Figure 28 shows one possible configuration using an RF transformer. Datasheet performance, especially at
>1GHz input frequency, can only be obtained with a carefully designed differential drive path to the ADC.
R₀
50 W
Z₀
50 W
AIN
AC Signal
Source
R
100 W
ADS5400
AIN
1:1
Figure 28. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer
Voltage Reference
The 2V voltage reference is provided internal to the ADS5400. A VCM (voltage common mode) pin is provided
as an output for use in dc-coupled applications, equal to the AVDD5 supply divided by 2. This provides the
analog input common mode voltage to a driving circuit so that the common mode is setup properly. Some
systems may prefer the use of an external voltage reference. This mode can be enabled by pulling the
ENEXTREF pin high. In this mode, an external reference can be driven onto the VREF pin, which is normally
expecting 2V.
Analog Input Over-Range Recovery Error
An over-range condition occurs if the analog input voltage exceeds the full-scale range of the converter (0dBFS).
To test recovery from an over-range, the ADC analog input is injected with a sinusoidal input frequency exactly at
CLKIN/4 (a four-point sinusoid at the digital outputs). The four sample points of each period occur at the top, mid-
scale, bottom and mid-scale of the sinusoid (clipped by the ADC when over-ranged to all 0s or all 1s). Once the
amplitude exceeds 0dBFS, the top and bottom of the sinusoidal input becomes out of range, while the mid-scale
point is always in-range and measureable with ADC output codes. The graph in Figure 29 indicates the amount
of error from the expected mid-scale value of 2048 that occurs after negative over-range (bottom of sinusoid) and
positive over-range (top of sinusoid). This equates to the amount of error in a valid sample 1 clock cycle after an
over-range occurs, as a function of input amplitude.
25
After Positive
20
Over-range
200MSPS (5ns)
15
After Negative
Over-range
10
400MSPS (2.5ns)
After Positive
Over-range
1GSPS (1ns)
5
0
−5
−10
−15
−20
−25
−1
After Positive
Over-range
400MSPS (2.5ns)
After Negative
Over-range
1GSPS (1ns)
After Negative
Over-range
200MSPS (5ns)
0
1
2
3
4
5
Analog Input Amplitude − dBFS
6
G023
Figure 29. Recovery Error 1 Clock Cycle After Over-Range vs Input Amplitude
32
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