ADS5400-SP Datasheet, PDF (7/46 Pages) Texas Instruments – 12-Bit, 1-GSPS Analog-to-Digital Converter

ADS5400-SP
www.ti.com
SLAS669C – SEPTEMBER 2010 – REVISED AUGUST 2012
TIMING CHARACTERISTICS⁽¹⁾ (continued)
Typical values at T_A = 25°C, Min and Max values over full temperature range T_C,MIN = –55°C to T_C,MAX = 125°C,
sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 V_PP differential clock
(unless otherwise noted)
PARAMETER
TEST CONDITIONS/NOTES
LVDS OUTPUT TIMING (DATA, CLKOUT, OVR/SYNCOUT)⁽²⁾
MIN
TYP
MAX UNIT
t_CLK
t_CLKH
t_CLKL
t_PD-CLKDIV2
Clock period
Clock pulse duration, high
Clock pulse duration, low
Clock propagation delay
Assuming worst case 45/55 duty cycle
Assuming worst case 55/45 duty cycle
CLKIN rising to CLKOUT rising in divide by 2
mode
1
0.45
0.45
1200
10 ns
ns
ns
ps
t_PD-CLKDIV4 Clock propagation delay
CLKIN rising to CLKOUT rising in divide by 4
mode
1200
ps
t_PD-ADATA
t_PD-BDATA
Bus A data propagation
delay
Bus B data propagation
delay
CLKIN falling to Data Output transition
1400
ps
1400
ps
t_SU-SBM ⁽³⁾
Setup time, single bus mode
Data valid to CLKOUT edge, 50% CLKIN duty
cycle
290 (t_CLK/2) - 185
ps
t_H-SBM
Hold time, single bus mode
CLKOUT edge to Data invalid, 50% CLKIN duty
cycle
410 (t_CLK/2) - 65
ps
t_SU-DBM
Setup time, dual bus mode
Data valid to CLKOUT edge, 50% CLKIN duty
cycle
550
t_CLK - 425
ps
t_H-DBM
Hold time, dual bus mode
CLKOUT edge to Data invalid, 50% CLKIN duty
cycle
1150
t_CLK + 175
ps
t_r
LVDS output rise time
t_f
LVDS output fall time
LVDS INPUT TIMING (RESETIN)
Measured 20% to 80%
400
ps
400
ps
t_RSU
RESET setup time
RESETP going HIGH to CLKINP going LOW
325
ps
t_RH
RESET hold time
CLKINP going LOW to RESETP going LOW
325
ps
RESET input capacitance Differential
1
pF
RESET input current
±1
µA
SERIAL INTERFACE TIMING
t_S-SDENB
t_H-SDENB
t_S-SDIO
t_H-SDIO
f_SCLK
t_SCLK
t_SCLKH
t_SCLKL
t_r
t_f
t_DDATA
Setup time, serial enable
Hold time, serial enable
Setup time, SDIO
Hold time, SDIO
Frequency
SCLK period
Minimum SCLK high time
Minimum SCLK low time
Rise time
Fall time
Data output delay
SDENB falling to SCLK rising
SCLK falling to SENDB rising
SDIO valid to SCLK rising
SCLK rising to SDIO transition
10pF
10pF
Data output (SDO/SDIO) delay after SCLK
falling, 10pF load
20
25
10
10
100
40
40
10
10
75
ns
ns
ns
ns
10 MHz
ns
ns
ns
ns
ns
ns
(2) LVDS output timing measured with a differential 100Ω load placed ~4 inches from the ADS5400. Measured differential load capacitance
is 3.5pF. Measurement probes and other parasitics add ~1pF. Total approximate capacitive load is 4.5pF differential. All timing
parameters are relative to the device pins, with the loading as stated.
(3) In single bus mode at 1GSPS (1ns clock), the minimum output setup/hold times over process and temperature provide a minimum
700ps of data valid window, with 300ps of uncertainity.
Copyright © 2010–2012, Texas Instruments Incorporated
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