ADC12130_14 Datasheet, PDF (9/52 Pages) Texas Instruments – ADC12130/ADC12132/ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold

ADC12130, ADC12132, ADC12138
www.ti.com
SNAS098G – MARCH 2000 – REVISED MARCH 2013
DC and Logic Electrical Characteristics (continued)
The following specifications apply for (V⁺ = V_A+ = V_D+ = +5V, V_REF+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V⁺ = V_A+ = V_D+ = +3.3V, V_REF+ = +2.5V and fully-differential input with fixed 1.250V common-
mode voltage), V_REF− = 0V, 12-bit + sign conversion mode⁽¹⁾, source impedance for analog inputs, V_REF− and V_REF+ ≤ 25Ω,
f_CK = f_SK = 5 MHz, and 10 (t_CK) acquisition time unless otherwise specified. Boldface limits apply for T_A = T_J = T_MIN to T_MAX;
all other limits T_A = T_J = 25°C. ^(2)(3)(4)
Parameter
Test Conditions
Typical
(5)
V⁺ = V_A+ =
V_D+ = 3.3V
Limits ⁽⁶⁾
V⁺ = V_A+ =
V_D+ = 5V
Limits ⁽⁶⁾
Units
(Limits)
POWER SUPPLY CHARACTERISTICS
Awake (Active)
1.5
2.5
mA (max)
I_D+
Digital Supply Current
CS = HIGH, Powered Down,
CCLK on
600
μA
CS = HIGH, Powered Down,
CCLK off
20
μA
Awake (Active)
3.0
4.0
mA (max)
I_A+
Positive Analog Supply Current
CS = HIGH, Powered Down,
10
CCLK on
μA
CS = HIGH, Powered Down,
0.1
CCLK off
μA
CS = HIGH, Powered Down,
CCLK on
70
μA
I_REF
Reference Input Current
CS = HIGH, Powered Down,
CCLK off
0.1
μA
AC Electrical Characteristics
The following specifications apply for (V⁺ = V_A+ = V_D+ = +5V, V_REF+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V⁺ = V_A+ = V_D+ = +3.3V, V_REF+ = +2.5V and fully-differential input with fixed 1.250V common-
mode voltage), V_REF− = 0V, 12-bit + sign conversion mode⁽¹⁾, source impedance for analog inputs, V_REF− and V_REF+ ≤ 25Ω,
f_CK = f_SK = 5 MHz, and 10 (t_CK) acquisition time unless otherwise specified. Boldface limits apply for T_A = T_J = T_MIN to T_MAX;
all other limits T_A = T_J = 25°C. ⁽²⁾
Parameter
Test Conditions
Typical ⁽³⁾
Limits ⁽⁴⁾
Units (Limits)
f_CK
Conversion Clock (CCLK) Frequency
10
5
MHz (max)
1
MHz (min)
f_SK
Serial Data Clock SCLK Frequency
10
5
MHz (max)
0
Hz (min)
Conversion Clock Duty Cycle
40
% (min)
60
% (max)
Serial Data Clock Duty Cycle
40
% (min)
60
% (max)
t_C
Conversion Time
12-Bit + Sign or 12-Bit
44(t_CK)
44(t_CK)
8.8
(max)
μs (max)
(1) The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device.
Therefore, the output data from these modes are not an indication of the accuracy of a conversion result.
(2) Timing specifications are tested at the TTL logic levels, V_OL = 0.4V for a falling edge and V_OL = 2.4V for a rising edge. TRI-STATE
output voltage is forced to 1.4V.
(3) Typical figures are at T_J = T_A = 25°C and represent most likely parametric norm.
(4) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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