ADC12130_14 Datasheet, PDF (31/52 Pages) Texas Instruments – ADC12130/ADC12132/ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold

ADC12130, ADC12132, ADC12138
www.ti.com
SNAS098G – MARCH 2000 – REVISED MARCH 2013
APPLICATION INFORMATION
NOTE: Some of the device/package combinations are obsolete and are shown and described here for
reference only. Please see the TI web site for availability.
1.0 DIGITAL INTERFACE
1.1 Interface Concepts
The example in Figure 65 shows a typical sequence of events after the power is applied to the ADC12130/2/8:
Figure 65. Typical Power Supply Power Up Sequence
The first instruction input to the ADC via DI initiates Auto Cal. The data output on DO at that time is meaningless
and is completely random. To determine whether the Auto Cal has been completed, a read status instruction
should be issued to the ADC. Again the data output at that time has no significance since the Auto Cal procedure
modifies the data in the output shift register. To retrieve the status information, an additional read status
instruction should be issued to the ADC. At this time the status data is available on DO. If the Cal signal in the
status word is low, Auto Cal has been completed. Therefore, the next instruction issued can start a conversion.
The data output at this time is again status information.
To keep noise from corrupting the conversion, status can not be read during a conversion. If CS is strobed and is
brought low during a conversion, that conversion is prematurely ended. EOC can be used to determine the end
of a conversion or the ADC controller can keep track in software of when it would be appropriate to communicate
to the ADC again. Once it has been determined that the ADC has completed a conversion, another instruction
can be transmitted to the ADC. The data from this conversion can be accessed when the next instruction is
issued to the ADC.
Note, when CS is low continuously it is important to transmit the exact number of SCLK cycles, as shown in the
timing diagrams. Not doing so will desynchronize the serial communication to the ADC. (See 1.3 CS Low
Continuously Considerations.)
1.2 Changing Configuration
The configuration of the ADC12130/2/8 on power up defaults to 12-bit plus sign resolution, 12- or 13-bit MSB
First, 10 CCLK acquisition time, user mode, no Auto Cal, no Auto Zero, and power up mode. Changing the
acquisition time and turning the sign bit on and off requires an 8-bit instruction to be issued to the ADC. This
instruction will not start a conversion. The instructions that select a multiplexer address and format the output
data do start a conversion. Figure 66 describes an example of changing the configuration of the ADC12130/2/8.
During I/O sequence 1, the instruction at DI configures the ADC to do a conversion with 12-bit +sign resolution.
Notice that, when the 6 CCLK Acquisition and Data Out without Sign instructions are issued to the ADC, I/O
sequences 2 and 3, a new conversion is not started. The data output during these instructions is from conversion
N, which was started during I/O sequence 1. The Figure 62 describes in detail the sequence of events necessary
for a Data Out without Sign, Data Out with Sign, or 6/10/18/34 CCLK Acquisition time mode selection. Table 4
describes the actual data necessary to be loaded into the ADC to accomplish this configuration modification. The
next instruction, shown in Figure 66, issued to the ADC starts conversion N+1 with 16-bit format and 12 bits of
resolution formatted MSB first. Again the data output during this I/O cycle is the data from conversion N.
The number of SCLKs applied to the ADC during any conversion I/O sequence should vary in accord with the
data out word format chosen during the previous conversion I/O sequence. The various formats and resolutions
available are shown in Table 1. In Figure 66, since 16-bit without sign MSB first format was chosen during I/O
sequence 4, the number of SCLKs required during I/O sequence 5 is sixteen. In the following I/O sequence the
format changes to 12-bit without sign MSB first; therefore the number of SCLKs required during I/O sequence 6
changes accordingly to 12.
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