TM4C1231D5PM Datasheet, PDF (893/1145 Pages) Texas Instruments – Tiva™ TM4C1231D5PM Microcontroller

Tiva^™ TM4C1231D5PM Microcontroller
Bit/Field
4
3:2
1
0
Name
RXMIS
reserved
CTSMIS
reserved
Type
RO
RO
RO
RO
Reset
0
0
0
0
Description
UART Receive Masked Interrupt Status
Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to passing through
the specified receive FIFO level.
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register
or by reading data from the receive FIFO until it becomes less than the
trigger level, if the FIFO is enabled, or by reading a single byte if the
FIFO is disabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Clear to Send Modem Masked Interrupt Status
Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to Clear to Send.
This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 12, 2014
893
Texas Instruments-Production Data