TM4C1231D5PM Datasheet, PDF (488/1145 Pages) Texas Instruments – Tiva™ TM4C1231D5PM Microcontroller

Hibernation Module
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x06F
This address space is implemented as a 16x32-bit memory (64 bytes). It can be loaded by the
system processor in order to store state information and retains its state during a power cut operation
as long as a battery is present.
Note:
The Hibernation module registers are on the Hibernation module clock domain and have
special timing requirements. Software should make use of the WRC bit in the HIBCTL register
to ensure that the required timing gap has elapsed. If the WRC bit is clear, any attempted
write access is ignored. See “Register Access Timing” on page 460.
Note: If V_DD is arbitrarily removed while a HIBDATA register write operation is in progress, the
write operation must be retried after V_DD is reapplied.
Hibernation Data (HIBDATA)
Base 0x400F.C000
Offset 0x030-0x06F
Type RW, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RTD
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RTD
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit/Field
31:0
Name
RTD
Type
RW
Reset
-
Description
Hibernation Module NV Data
488
June 12, 2014
Texas Instruments-Production Data