TM4C1231D5PM Datasheet, PDF (490/1145 Pages) Texas Instruments – Tiva™ TM4C1231D5PM Microcontroller

Internal Memory
Figure 8-2 on page 490 illustrates the internal EEPROM block and control logic. The EEPROM block
is connected to the AHB bus.
Figure 8-2. EEPROM Block Diagram
EEPROM Control
EESIZE
EEBLOCK
EEOFFSET
EERDWR
EERDWRINC
EEDONE
EESUPP
EEUNLOCK
EEPROT
EEPASS0
EEPASS1
EEPASS2
EEINT
EEHIDE
EEDBGME
EEPROMPP
Security
Program
EEPROM Array
Block 0
Block 1
Block 2
Block 3
...
Block n
8.2
8.2.1
Functional Description
This section describes the functionality of the SRAM, ROM, Flash, and EEPROM memories.
Note: The μDMA controller can transfer data to and from the on-chip SRAM. However, because
the Flash memory and ROM are located on a separate internal bus, it is not possible to
transfer data from the Flash memory or ROM with the μDMA controller.
SRAM
The internal SRAM of the TM4C1231D5PM device is located at address 0x2000.0000 of the device
memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM
provides bit-banding technology in the processor. With a bit-band-enabled processor, certain regions
in the memory map (SRAM and peripheral space) can use address aliases to access individual bits
in a single, atomic operation. The bit-band base is located at address 0x2200.0000.
The bit-band alias is calculated by using the formula:
bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C
With the alias address calculated, an instruction performing a read/write to address 0x2202.000C
allows direct access to only bit 3 of the byte at address 0x2000.1000.
For details about bit-banding, see “Bit-Banding” on page 87.
490
June 12, 2014
Texas Instruments-Production Data