TMS320VC5416_17 Datasheet, PDF (89/98 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008
5.5.11.2 HPI16 Mode
Table 5-34 and Table 5-35 assume testing over recommended operating conditions and P = 0.5 *
processor clock (see Figure 5-32 through Figure 5-34). In the following tables, DS refers to the logical OR
of HCS, HDS1, and HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). These
timings are shown assuming that HDS is the signal controlling the transfer. See the TMS320C54x DSP
Reference Set,Volume 5: Enhanced Peripherals (literature number SPRU302) for additional information.
Table 5-34. HPI16 Mode Timing Requirements
t_su(HBV-DSL)
t_h(DSL-HBV)
t_su(HAV-DSH)
t_su(HAV-DSL)
t_h(DSH-HAV)
t_w(DSL)
t_w(DSH)
Setup time, HR/W valid before DS falling edge
Hold time, HR/W valid after DS falling edge
Setup time, address valid before DS rising edge (write)
Setup time, address valid before DS falling edge (read)
Hold time, address valid after DS rising edge
Pulse duration, DS low
Pulse duration, DS high
Memory accesses with no DMA activity.
t_c(DSH-DSH)
Cycle time, DS rising edge to Memory accesses with 16-bit DMA
next DS rising edge
activity.
Memory accesses with 32-bit DMA
activity.
t_su(HDV-DSH)W
Setup time, HD valid before DS rising edge
t_h(DSH-HDV)W
Hold time, HD valid after DS rising edge, write
(1) P = 0.5 * processor clock.
5416-120
5416-160
MIN
MAX
6
5
5
–(4P– 6)⁽¹⁾
1
30
10
Reads 10P + 30⁽¹⁾
Writes 10P + 10⁽¹⁾
Reads 16P + 30⁽¹⁾
Writes 16P + 10⁽¹⁾
Reads 24P + 30⁽¹⁾
Writes 24P + 10⁽¹⁾
8
2
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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