TMS320VC5416_17 Datasheet, PDF (81/98 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008
5.5.10.3 McBSP as SPI Master or Slave Timing
Table 5-24 to Table 5-31 assume testing over recommended operating conditions (see Figure 5-24,
Figure 5-25, Figure 5-26, and Figure 5-27).
Table 5-24. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)⁽¹⁾
5416-120
5416-160
MASTER
SLAVE
t_{su(BDRV-BCKXL)}
t_{h(BCKXL-BDRV)}
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
MIN MAX
MIN MAX
12
2 – 6P⁽²⁾
4
5 + 12P⁽²⁾
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = 0.5 * processor clock.
UNIT
ns
ns
Table 5-25. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)⁽¹⁾
PARAMETER
5416-120
5416-160
MASTER ⁽²⁾
SLAVE
UNIT
t_{h(BCKXL-BFXL)}
t_{d(BFXL-BCKXH)}
t_{d(BCKXH-BDXV)}
t_{dis(BCKXL-BDXHZ)}
Hold time, BFSX low after BCLKX low⁽³⁾
Delay time, BFSX low to BCLKX high⁽⁴⁾
Delay time, BCLKX high to BDX valid
Disable time, BDX high impedance following last data bit from
BCLKX low
MIN MAX
MIN
MAX
T–3 T+4
ns
C–4 C+3
ns
–4
5 6P + 2⁽⁵⁾ 10P + 17⁽⁵⁾ ns
C–2 C+3
ns
t_{dis(BFXH-BDXHZ)}
t_d(BFXL-BDXV)
Disable time, BDX high impedance following last data bit from
BFSX high
Delay time, BFSX low to BDX valid
2P– 4⁽⁵⁾ 6P + 17⁽⁵⁾ ns
4P+ 2⁽⁵⁾ 8P + 17⁽⁵⁾ ns
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) T = BCLKX period = (1 + CLKGDV) * 2P
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) *2P when CLKGDV is even
(3) FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input
on BFSX and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FRSRM = 2 for master McBSP
CLKXM = CLKRm = FSXM = FSRM = 0 for slave McBSP
(4) BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the
master clock (BCLKX).
(5) P = 0.5 * processor clock.
BCLKX
LSB
BFSX
BDX
Bit 0
BDR
Bit 0
MSB
t_{h(BCKXL-BFXL)}
t_{d(BFXL-BCKXH)}
t_{dis(BFXH-BDXHZ)}
t_{dis(BCKXL-BDXHZ)}
t_{su(BDRV-BCLXL)}
t_d(BFXL-BDXV)
t_{d(BCKXH-BDXV)}
Bit(n-1)
(n-2)
(n-3)
Bit(n-1)
t_{h(BCKXL-BDRV)}
(n-2)
(n-3)
(n-4)
(n-4)
Figure 5-24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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Electrical Specifications
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