TMS570LS0914_17 Datasheet, PDF (88/163 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

TMS570LS0914
SPNS225D – JUNE 2013 – REVISED NOVEMBER 2016
www.ti.com
6.20 Debug Subsystem
6.20.1 Block Diagram
The device contains an ICEPICK module (version C) to allow JTAG access to the scan chains (see
Figure 6-14).
TRST
TMS
TCK
RTCK
TDI
TDO
Boundary Scan
Interface
Boundary Scan
BSR/BSDL
Secondary Tap 0
DAP
APB Mux
AHB-AP
Debug APB
POM
To
SCR1
through A2A
From
PCR Bridge
Debug
ROM1
APB slave
Cortex
R4F
Secondary Tap 2
AJSM
Test Tap 0
eFuse Farm
Test Tap 1
PSCON
Figure 6-14. Debug Subsystem Block Diagram
6.20.2 Debug Components Memory Map
MODULE
NAME
CoreSight Debug ROM
Cortex-R4F Debug
Table 6-33. Debug Components Memory Map
FRAME CHIP
SELECT
CSCS0
CSCS1
FRAME ADDRESS RANGE
START
END
0xFFA0_0000 0xFFA0_0FFF
0xFFA0_1000 0xFFA0_1FFF
FRAME
SIZE
4KB
4KB
ACTUAL
SIZE
RESPONSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS
IN FRAME
4KB Reads return zeros, writes have no effect
4KB Reads return zeros, writes have no effect
6.20.3 JTAG Identification Code
The JTAG ID code for this device is the same as the device ICEPick Identification Code. For the JTAG ID
Code per silicon revision, see Table 6-34.
Table 6-34. JTAG ID Code
SILICON REVISION
Rev 0
Rev A
ID
0x0BB0302F
0x1BB0302F
88
System Information and Electrical Specifications
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