TMS570LS0914_17 Datasheet, PDF (84/163 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

TMS570LS0914
SPNS225D – JUNE 2013 – REVISED NOVEMBER 2016
www.ti.com
6.18 Reset/Abort/Error Sources
Table 6-32. Reset/Abort/Error Sources
ERROR SOURCE
CPU TRANSACTIONS
Precise write error (NCNB/Strongly Ordered)
Precise read error (NCB/Device or Normal)
Imprecise write error (NCB/Device or Normal)
Illegal instruction
MPU access violation
SRAM
B0 TCM (even) ECC single error (correctable)
B0 TCM (even) ECC double error (uncorrectable)
B0 TCM (even) uncorrectable error (that is, redundant address
decode)
B0 TCM (even) address bus parity error
B1 TCM (odd) ECC single error (correctable)
B1 TCM (odd) ECC double error (uncorrectable)
B1 TCM (odd) uncorrectable error (that is, redundant address
decode)
B1 TCM (odd) address bus parity error
FLASH WITH CPU BASED ECC
FMC correctable error - Bus1 and Bus2 interfaces (does not
include accesses to Bank 7)
FMC uncorrectable error - Bus1 and Bus2 accesses
(does not include address parity error)
FMC uncorrectable error - address parity error on Bus1
accesses
FMC correctable error - Accesses to Bank 7
FMC uncorrectable error - Accesses to Bank 7
DMA TRANSACTIONS
External imprecise error on read (Illegal transaction with ok
response)
External imprecise error on write (Illegal transaction with ok
response)
Memory access permission violation
Memory parity error
HET TU1 (HTU1)
NCNB (Strongly Ordered) transaction with slave error response
External imprecise error (Illegal transaction with ok response)
Memory access permission violation
Memory parity error
HET TU2 (HTU2)
NCNB (Strongly Ordered) transaction with slave error response
External imprecise error (Illegal transaction with ok response)
Memory access permission violation
Memory parity error
CPUMODE
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ERROR RESPONSE
ESM HOOKUP
GROUP.CHANNE
L
Precise Abort (CPU)
N/A
Precise Abort (CPU)
N/A
Imprecise Abort (CPU)
N/A
Undefined Instruction Trap
(CPU) ⁽¹⁾
N/A
Abort (CPU)
N/A
ESM
1.26
Abort (CPU), ESM => →
nERROR
3.3
ESM => NMI => nERROR
2.6
ESM => NMI => nERROR
2.10
ESM
1.28
Abort (CPU), ESM =>
nERROR
3.5
ESM => NMI => nERROR
2.8
ESM => NMI => nERROR
2.12
ESM
1.6
Abort (CPU), ESM =>
nERROR
3.7
ESM => NMI => nERROR
2.4
ESM
1.35
ESM
1.36
ESM
1.5
ESM
1.13
ESM
1.2
ESM
1.3
Interrupt => VIM
N/A
Interrupt => VIM
N/A
ESM
1.9
ESM
1.8
Interrupt => VIM
N/A
Interrupt => VIM
N/A
ESM
1.9
ESM
1.8
(1) The Undefined Instruction TRAP is not detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage of
the CPU.
84
System Information and Electrical Specifications
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