TMS320C6678_14 Datasheet, PDF (88/249 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691E—March 2014
3.3.14 IPC Acknowledgement Registers (IPCARx)
IPCARx are the IPC interrupt-acknowledgement registers to facilitate inter-CorePac core interrupts.
The C6678 has eight IPCARx registers (IPCAR0 through IPCAR7). These registers also provide a Source ID facility
by which up to 28 different sources of interrupts can be identified. Allocation of source bits to source processor and
meaning is entirely based on software convention. The register field descriptions are shown in the following tables.
Virtually anything can be a source for these registers as this is completely controlled by software. Any master that
has access to BOOTCFG module space can write to these registers. The IPC Acknowledgement Register is shown in
Figure 3-13 and described in Table 3-15.
Figure 3-13 IPC Acknowledgement (IPCARx) Registers
31
30
29
28
27
8
7
6
5
4
3
0
SRCC27 SRCC26 SRCC25 SRCC24
SRCC23 – SRCC4
SRCC3 SRCC2 SRCC1 SRCC0
Reserved
RW-0 RW-0 RW-0 RW-0
RW-0 (per bit field)
RW-0 RW-0 RW-0 RW-0
R-0000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-15 IPC Acknowledgement Registers (IPCARx) Field Descriptions
Bit Field
31-4 SRCCx
3-0 Reserved
End of Table 3-15
Description
Interrupt source acknowledgement.
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Clears both SRCCx and the corresponding SRCSx
Reserved
3.3.15 IPC Generation Host Register (IPCGRH)
The IPCGRH register facilitates interrupts to external hosts. Operation and use of the IPCGRH register is the same
as for other IPCGR registers. The interrupt output pulse created by the IPCGRH register appears on device pin
HOUT.
The host interrupt output pulse is stretched so that it is asserted for four bootcfg clock (CPU/6) cycles followed by a
deassertion of four bootcfg clock cycles. Generating the pulse results in a pulse-blocking window that is eight
CPU/6-cycles long. Back to back writes to the IPCRGH register with the IPCG bit (bit 0) set, generates only one pulse
if the back-to-back writes to IPCGRH are less than the eight CPU/6 cycle window -- the pulse blocking window. In
order to generate back-to-back pulses, the back-to-back writes to the IPCGRH register must be greater than eight
CPU/6 cycle window. The IPC Generation Host Register is shown in Figure 3-14 and described in Table 3-16.
Figure 3-14 IPC Generation (IPCGRH) Registers
31
30
29
28
27
8
7
6
5
4
3
1
0
SRCS27 SRCS26 SRCS25 SRCS24
SRCS23 – SRCS4
SRCS3 SRCS2 SRCS1 SRCS0
Reserved
IPCG
RW-0 RW-0 RW-0 RW-0
RW-0 (per bit field)
RW-0 RW-0 RW-0 RW-0
R-000
RW-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
88 Device Configuration
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