TMS320C6678_14 Datasheet, PDF (137/249 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691E—March 2014
7.5.4 Local Reset
The local reset can be used to reset a particular CorePac without resetting any other chip components.
Local reset is initiated by the following (for more details see the Phase Locked Loop (PLL) for KeyStone Devices User
Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72:
• LRESET pin
• Watchdog timer should cause one of the below based on the setting of the CORESEL[2:0] and RSTCFG
register in the PLL controller. See ‘‘Reset Configuration Register (RSTCFG)’’ on page 148 and ‘‘CIC Registers’’
on page 183:
– Local reset
– NMI
– NMI followed by a time delay and then a local reset for the CorePac selected
– Hard Reset by requesting reset via PLLCTL
• LPSC MMRs (memory-mapped registers)
7.5.5 Reset Priority
If any of the above reset sources occur simultaneously, the PLLCTL processes only the highest priority reset request.
The reset request priorities are as follows (high to low):
• Power-on reset
• Hard/soft reset
7.5.6 Reset Controller Register
The reset controller register are part of the PLLCTL MMRs. All C6678 device-specific MMRs are covered in Section
7.6.3 ‘‘Main PLL Control Register’’ on page 150. For more details on these registers and how to program them, see
the Phase Locked Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’
on page 72.
Copyright 2014 Texas Instruments Incorporated
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Peripheral Information and Electrical Specifications 137