TMS320C6678_14 Datasheet, PDF (167/249 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691E—March 2014
Figure 7-32 shows the mapping of system events. For more information on the Interrupt Controller, see the C66x
DSP CorePac User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72.
Figure 7-32 TMS320C6678 System Event Inputs — C66x CorePac Primary Interrupts (Sheet 1 of 4)
Input Event Number Interrupt Event
Description
0
EVT0
Event combiner 0 output
1
EVT1
Event combiner 1 output
2
EVT2
Event combiner 2 output
3
EVT3
4
TETBHFULLINTn ⁽¹⁾
5
TETBFULLINTn ⁽¹⁾
6
TETBACQINTn ⁽¹⁾
7
TETBOVFLINTn ⁽¹⁾
8
TETBUNFLINTn ⁽¹⁾
Event combiner 3 output
TETB is half full
TETB is full
Acquisition has been completed
Overflow condition interrupt
Underflow condition interrupt
9
EMU_DTDMA
10
MSMC_mpf_errorn ⁽²⁾
ECM interrupt for:
1. Host scan access
2. DTDMA transfer complete
3. AET interrupt
Memory protection fault indicators for local core
11
EMU_RTDXRX
RTDX receive complete
12
EMU_RTDXTX
RTDX transmit complete
13
IDMA0
IDMA channel 0 interrupt
14
IDMA1
IDMA channel 1 interrupt
15
SEMERRn ⁽³⁾
Semaphore error interrupt
16
SEMINTn ⁽³⁾
Semaphore interrupt
17
PCIExpress_MSI_INTn ⁽⁴⁾
Message signaled interrupt mode
18
TSIP0_ERRINT[n] ⁽⁵⁾
TSIP0 receive/transmit error interrupt
19
TSIP1_ERRINT[n] ⁽⁵⁾
TSIP1 receive/transmit error interrupt
20
INTDST(n+16) ⁽⁶⁾
SRIO Interrupt
21
CIC0_OUT(32+0+11*n) ⁽⁷⁾ Or CIC1_OUT(32+0+11*(n-4)) ⁽⁷⁾
Interrupt Controller output
22
CIC0_OUT(32+1+11*n) ⁽⁷⁾ Or CIC1_OUT(32+1+11*(n-4)) ⁽⁷⁾
Interrupt Controller output
23
CIC0_OUT(32+2+11*n) ⁽⁷⁾ Or CIC1_OUT(32+2+11*(n-4)) ⁽⁷⁾
Interrupt Controller output
24
CIC0_OUT(32+3+11*n) ⁽⁷⁾ Or CIC1_OUT(32+3+11*(n-4)) ⁽⁷⁾
Interrupt Controller output
25
CIC0_OUT(32+4+11*n) ⁽⁷⁾ Or CIC1_OUT(32+4+11*(n-4)) ⁽⁷⁾
Interrupt Controller output
26
CIC0_OUT(32+5+11*n) ⁽⁷⁾ Or CIC1_OUT(32+5+11*(n-4)) ⁽⁷⁾
Interrupt Controller output
27
CIC0_OUT(32+6+11*n) ⁽⁷⁾ Or CIC1_OUT(32+6+11*(n-4)) ⁽⁷⁾
Interrupt Controller output
28
CIC0_OUT(32+7+11*n) ⁽⁷⁾ Or CIC1_OUT(32+7+11*(n-4)) ⁽⁷⁾
Interrupt Controller output
29
CIC0_OUT(32+8+11*n) ⁽⁷⁾ Or CIC1_OUT(32+8+11*(n-4)) ⁽⁷⁾
Interrupt Controller output
30
CIC0_OUT(32+9+11*n) ⁽⁷⁾ Or CIC1_OUT(32+9+11*(n-4)) ⁽⁷⁾
Interrupt Controller output
31
CIC0_OUT(32+10+11*n) ⁽⁷⁾ Or CIC1_OUT(32+10+11*(n-4)) ⁽⁷⁾ Interrupt Controller output
32
QM_INT_LOW_0
QM Interrupt for 0~31 Queues
33
QM_INT_LOW_1
QM Interrupt for 32~63 Queues
34
QM_INT_LOW_2
QM Interrupt for 64~95 Queues
35
QM_INT_LOW_3
QM Interrupt for 96~127 Queues
36
QM_INT_LOW_4
QM Interrupt for 128~159 Queues
37
QM_INT_LOW_5
QM Interrupt for 160~191 Queues
38
QM_INT_LOW_6
QM Interrupt for 192~223 Queues
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