LM3S1751_16 Datasheet, PDF (88/679 Pages) Texas Instruments – Stellaris LM3S1751 Microcontroller

The Cortex-M3 Processor
2.8
In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers
an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to
cause exception entry. For more information about SYSCTRL, see page 126.
Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 2-13 on page 88 lists the
supported instructions.
Note: In Table 2-13 on page 88:
■ Angle brackets, <>, enclose alternative forms of the operand
■ Braces, {}, enclose optional operands
■ The Operands column is not exhaustive
■ Op2 is a flexible second operand that can be either a register or a constant
■ Most instructions can use an optional condition code suffix
For more information on the instructions and operands, see the instruction descriptions in
the Cortex™-M3/M4 Instruction Set Technical User's Manual.
Table 2-13. Cortex-M3 Instruction Summary
Mnemonic
ADC, ADCS
ADD, ADDS
ADD, ADDW
ADR
AND, ANDS
ASR, ASRS
B
BFC
BFI
BIC, BICS
BKPT
BL
BLX
BX
CBNZ
CBZ
CLREX
CLZ
CMN
CMP
CPSID
Operands
{Rd,} Rn, Op2
{Rd,} Rn, Op2
{Rd,} Rn , #imm12
Rd, label
{Rd,} Rn, Op2
Rd, Rm, <Rs|#n>
label
Rd, #lsb, #width
Rd, Rn, #lsb, #width
{Rd,} Rn, Op2
#imm
label
Rm
Rm
Rn, label
Rn, label
-
Rd, Rm
Rn, Op2
Rn, Op2
i
CPSIE
i
DMB
-
DSB
-
Brief Description
Add with carry
Add
Add
Load PC-relative address
Logical AND
Arithmetic shift right
Branch
Bit field clear
Bit field insert
Bit clear
Breakpoint
Branch with link
Branch indirect with link
Branch indirect
Compare and branch if non-zero
Compare and branch if zero
Clear exclusive
Count leading zeros
Compare negative
Compare
Change processor state, disable
interrupts
Change processor state, enable
interrupts
Data memory barrier
Data synchronization barrier
Flags
N,Z,C,V
N,Z,C,V
N,Z,C,V
-
N,Z,C
N,Z,C
-
-
-
N,Z,C
-
-
-
-
-
-
-
-
N,Z,C,V
N,Z,C,V
-
-
-
-
88
July 15, 2014
Texas Instruments-Production Data