TMS570LS1115 Datasheet, PDF (86/175 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

TMS570LS1115
SPNS189B – OCTOBER 2012 – REVISED FEBRUARY 2015
www.ti.com
EMIF_nCS[3:2]
SETUP
STROBE
Extended Due to EMIF_WAIT STROBE HOLD
EMIF_BA[1:0]
EMIF_ADDR[12:0]
EMIF_DATA[15:0]
EMIF_nWE
28
25
EMIF_WAIT
2
Asserted
2
Deasserted
Figure 6-15. EMIFnWAIT Write Timing Requirements
Table 6-27. EMIF Asynchronous Memory Timing Requirements⁽¹⁾
NO.
Value
Unit
MIN
NOM
MAX
Reads and Writes
E
EMIF clock period
11
ns
2
t_{w(EM_WAIT)}
Pulse duration, EMIF_nWAIT
2E
ns
assertion and deassertion
Reads
12 t_{su(EMDV-EMOEH)}
Setup time, EMIF_DATA[15:0]
9
ns
valid before EMIFnOE high
13 t_{h(EMOEH-EMDIV)}
Hold time, EMIF_DATA[15:0]
0
ns
valid after EMIF_nOE high
14 t_{su(EMOEL-EMWAIT)}
Setup Time, EMIF_nWAIT
4E+9
ns
asserted before end of Strobe
Phase ⁽²⁾
Writes
28 t_{su(EMWEL-EMWAIT)}
Setup Time, EMIF_nWAIT
4E+14
ns
asserted before end of Strobe
Phase ⁽²⁾
(1) E = EMIF_CLK period in ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended
wait states. Figure 6-13 and Figure 6-15 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
86
System Information and Electrical Specifications
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