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TMS570LS1115 Datasheet, PDF (1/175 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller | |||
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TMS570LS1115
SPNS189B â OCTOBER 2012 â REVISED FEBRUARY 2015
TMS570LS1115 16- and 32-Bit RISC Flash Microcontroller
1 Device Overview
1.1 Features
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⢠High-Performance Automotive-Grade
Microcontroller for Safety-Critical Applications
â Dual CPUs Running in Lockstep
â ECC on Flash and RAM Interfaces
â Built-In Self-Test (BIST) for CPU and On-chip
RAMs
â Error Signaling Module With Error Pin
â Voltage and Clock Monitoring
⢠ARM® Cortex®-R4F 32-Bit RISC CPU
â 1.66 DMIPS/MHz With 8-Stage Pipeline
â FPU With Single- and Double-Precision
â 12-Region Memory Protection Unit (MPU)
â Open Architecture With Third-Party Support
⢠Operating Conditions
â Up to 180-MHz System Clock
â Core Supply Voltage (VCC): 1.14 to 1.32 V
â I/O Supply Voltage (VCCIO): 3.0 to 3.6 V
⢠Integrated Memory
â 1MB of Program Flash With ECC
â 128KB of RAM With ECC
â 64KB of Flash for Emulated EEPROM With
ECC
⢠16-Bit External Memory Interface (EMIF)
⢠Common Platform Architecture
â Consistent Memory Map Across Family
â Real-Time Interrupt (RTI) Timer (OS Timer)
â 128-Channel Vectored Interrupt Module (VIM)
â 2-Channel Cyclic Redundancy Checker (CRC)
⢠Direct Memory Access (DMA) Controller
â 16 Channels and 32 Control Packets
â Parity Protection for Control Packet RAM
â DMA Accesses Protected by Dedicated MPU
⢠Frequency-Modulated Phase-Locked Loop
(FMPLL) With Built-In Slip Detector
⢠Separate Nonmodulating PLL
⢠IEEE 1149.1 JTAG, Boundary Scan and ARM
CoreSight⢠Components
⢠Advanced JTAG Security Module (AJSM)
⢠Calibration Capabilities
â Parameter Overlay Module (POM)
⢠16 General-Purpose Input/Output (GPIO) Pins
Capable of Generating Interrupts
⢠Enhanced Timing Peripherals for Motor Control
â 7 Enhanced Pulse Width Modulator (ePWM)
Modules
â 6 Enhanced Capture (eCAP) Modules
â 2 Enhanced Quadrature Encoder Pulse (eQEP)
Modules
⢠Two Next Generation High-End Timer (N2HET)
Modules
â N2HET1: 32 Programmable Channels
â N2HET2: 18 Programmable Channels
â 160-Word Instruction RAM Each With Parity
Protection
â Each N2HET Includes Hardware Angle
Generator
â Dedicated High-End Timer Transfer Unit (HTU)
for Each N2HET
⢠Two 12-Bit Multibuffered Analog-to-Digital
Converter (MibADC) Modules
â ADC1: 24 Channels
â ADC2: 16 Channels Shared With ADC1
â 64 Result Buffers Each With Parity Protection
⢠Multiple Communication Interfaces
â FlexRay Controller With 2 Channels
⢠8KB of Message RAM With Parity Protection
⢠Dedicated FlexRay Transfer Unit (FTU)
â Three CAN Controllers (DCANs)
⢠64 Mailboxes Each With Parity Protection
⢠Compliant to CAN Protocol Version 2.0A and
2.0B
â Inter-Integrated Circuit (I2C)
â Three Multibuffered Serial Peripheral Interface
(MibSPI) Modules
⢠128 Words Each With Parity Protection
⢠8 Transfer Groups
â Up to Two Standard Serial Peripheral Interface
(SPI) Modules
â Two UART (SCI) Interfaces, One With Local
Interconnect Network (LIN 2.1) Interface
Support
⢠Packages
â 144-Pin Quad Flatpack (PGE) [Green]
â 337-Ball Grid Array (ZWT) [Green]
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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