TMS320F28335_016 Datasheet, PDF (86/201 Pages) Texas Instruments – Digital Signal Controllers (DSCs)

TMS320F28335, TMS320F28334, TMS320F28333, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439N – JUNE 2007 – REVISED OCTOBER 2016
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5.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
Table 5-51. External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
PARAMETER
MIN
MAX UNIT
t_{d(XCOH-XZCSL)}
t_{d(XCOHL-XZCSH)}
t_d(XCOH-XA)
t_{d(XCOHL-XRDL)}
t_{d(XCOHL-XRDH)}
t_h(XA)XZCSH
t_h(XA)XRD
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
–1
– 1.5
(1)
(1)
1 ns
0.5 ns
1.5 ns
0.5 ns
0.5 ns
ns
ns
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus, except XA0, which remains high. This
includes alignment cycles.
Table 5-52. External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
t_a(A)
Access time, read data from address valid
t_a(XRD)
Access time, read data valid from XRD active low
t_su(XD)XRD
Setup time, read data valid before XRD strobe inactive high
t_h(XD)XRD
Hold time, read data valid after XRD inactive high
(1) LR = Lead period, read access. AR = Active period, read access. See Table 5-46.
MIN
MAX UNIT
(LR + AR) – 16 ⁽¹⁾
ns
AR – 14 ⁽¹⁾
ns
14
ns
0
ns
Table 5-53. Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)⁽¹⁾
MIN
MAX UNIT
t_{su(XRDYsynchL)XCOHL}
t_{h(XRDYsynchL)}
t_{e(XRDYsynchH)}
Setup time, XREADY (synchronous) low before XCLKOUT high/low
Hold time, XREADY (synchronous) low
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
12
ns
6
ns
3 ns
t_{su(XRDYsynchH)XCOHL}
Setup time, XREADY (synchronous) high before XCLKOUT high/low
12
ns
t_{h(XRDYsynchH)XZCSH}
Hold time, XREADY (synchronous) held high after zone chip select high
0
ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 5-31:
E = (XRDLEAD + XRDACTIVE) t_c(XTIM)
When first sampled, if XREADY (synchronous) is found to be high, then the access will finish. If XREADY (synchronous) is found to be
low, it is sampled again each t_c(XTIM) until it is found to be high.
For each sample (n) the setup time (F) with respect to the beginning of the access can be calculated as:
F = (XRDLEAD + XRDACTIVE +n − 1) t_c(XTIM) − t_{su(XRDYsynchL)XCOHL}
where n is the sample number: n = 1, 2, 3, and so forth.
Table 5-54. Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
t_{su(XRDYAsynchL)XCOHL}
t_{h(XRDYAsynchL)}
t_{e(XRDYAsynchH)}
t_{su(XRDYAsynchH)XCOHL}
t_{h(XRDYasynchH)XZCSH}
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
Hold time, XREADY (asynchronous) low
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
Hold time, XREADY (asynchronous) held high after zone chip select high
MIN
MAX UNIT
11
ns
6
ns
3 ns
11
ns
0
ns
86
Specifications
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