TMS320F28335_016 Datasheet, PDF (77/201 Pages) Texas Instruments – Digital Signal Controllers (DSCs)

www.ti.com
TMS320F28335, TMS320F28334, TMS320F28333, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439N – JUNE 2007 – REVISED OCTOBER 2016
5.9.6 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the
Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF
zone. Table 5-46 shows the relationship between the parameters configured in the XTIMING register and
the duration of the pulse in terms of XTIMCLK cycles.
Table 5-46. Relationship Between Parameters Configured in XTIMING and Duration of Pulse
DESCRIPTION
X2TIMING = 0
DURATION (ns)^{(1) (2)}
X2TIMING = 1
LR
Lead period, read access
AR
Active period, read access
TR
Trail period, read access
LW
Lead period, write access
AW
Active period, write access
TW
Trail period, write access
XRDLEAD × t_c(XTIM)
(XRDACTIVE + WS + 1) × t_c(XTIM)
XRDTRAIL × t_c(XTIM)
XWRLEAD × t_c(XTIM)
(XWRACTIVE + WS + 1) × t_c(XTIM)
XWRTRAIL × t_c(XTIM)
(XRDLEAD × 2) × t_c(XTIM)
(XRDACTIVE × 2 + WS + 1) × t_c(XTIM)
(XRDTRAIL × 2) × t_c(XTIM)
(XWRLEAD × 2) × t_c(XTIM)
(XWRACTIVE × 2 + WS + 1) × t_c(XTIM)
(XWRTRAIL × 2) × t_c(XTIM)
(1) t_c(XTIM) − Cycle time, XTIMCLK
(2) WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY
(USEREADY = 0), then WS = 0.
Minimum wait-state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No
internal device hardware is included to detect illegal settings.
5.9.6.1 USEREADY = 0
If the XREADY signal is ignored (USEREADY = 0), then:
Lead:
LR ≥ t_c(XTIM)
LW ≥ t_c(XTIM)
These requirements result in the following XTIMING register configuration restrictions:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
≥1
≥0
≥0
≥1
≥0
≥0
Examples of valid and invalid timing when not sampling XREADY:
XRDLEAD XRDACTIVE XRDTRAIL
XWRLEAD XWRACTIVE
Invalid ⁽¹⁾
0
0
0
0
0
Valid
1
0
0
1
0
(1) No hardware to detect illegal XTIMING configurations
XWRTRAIL
0
0
X2TIMING
0, 1
X2TIMING
0, 1
0, 1
Copyright © 2007–2016, Texas Instruments Incorporated
Specifications
77
Submit Documentation Feedback
Product Folder Links: TMS320F28335 TMS320F28334 TMS320F28333 TMS320F28332 TMS320F28235
TMS320F28234 TMS320F28232