TM4C1231E6PM Datasheet, PDF (859/1133 Pages) Texas Instruments – Brown-Out Reset Control (PBORCTL), offset 0x030

Tiva^™ TM4C1231E6PM Microcontroller _{(identical to LM4F110E5QR)}
14.3.11
DMA Operation
The UART provides an interface to the μDMA controller with separate channels for transmit and
receive. The DMA operation of the UART is enabled through the UART DMA Control
(UARTDMACTL) register. When DMA operation is enabled, the UART asserts a DMA request on
the receive or transmit channel when the associated FIFO can transfer data. For the receive channel,
a single transfer request is asserted whenever any data is in the receive FIFO. A burst transfer
request is asserted whenever the amount of data in the receive FIFO is at or above the FIFO trigger
level configured in the UARTIFLS register. For the transmit channel, a single transfer request is
asserted whenever there is at least one empty location in the transmit FIFO. The burst request is
asserted whenever the transmit FIFO contains fewer characters than the FIFO trigger level. The
single and burst DMA transfer requests are handled automatically by the μDMA controller depending
on how the DMA channel is configured.
To enable DMA operation for the receive channel, set the RXDMAE bit of the DMA Control
(UARTDMACTL) register. To enable DMA operation for the transmit channel, set the TXDMAE bit
of the UARTDMACTL register. The UART can also be configured to stop using DMA for the receive
channel if a receive error occurs. If the DMAERR bit of the UARTDMACR register is set and a receive
error occurs, the DMA receive requests are automatically disabled. This error condition can be
cleared by clearing the appropriate UART error interrupt.
If DMA is enabled, then the μDMA controller triggers an interrupt when a transfer is complete. The
interrupt occurs on the UART interrupt vector. Therefore, if interrupts are used for UART operation
and DMA is enabled, the UART interrupt handler must be designed to handle the μDMA completion
interrupt.
See “Micro Direct Memory Access (μDMA)” on page 546 for more details about programming the
μDMA controller.
14.4
Initialization and Configuration
To enable and initialize the UART, the following steps are necessary:
1. Enable the UART module using the RCGCUART register (see page 323).
2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register (see page 319).
To find out which GPIO port to enable, refer to Table 20-5 on page 1084.
3. Set the GPIO AFSEL bits for the appropriate pins (see page 631). To determine which GPIOs to
configure, see Table 20-4 on page 1080.
4. Configure the GPIO current level and/or slew rate as specified for the mode selected (see
page 633 and page 641).
5. Configure the PMCn fields in the GPIOPCTL register to assign the UART signals to the appropriate
pins (see page 648 and Table 20-5 on page 1084).
To use the UART, the peripheral clock must be enabled by setting the appropriate bit in the
RCGCUART register (page 323). In addition, the clock to the appropriate GPIO module must be
enabled via the RCGCGPIO register (page 319) in the System Control module. To find out which
GPIO port to enable, refer to Table 20-5 on page 1084.
This section discusses the steps that are required to use a UART module. For this example, the
UART clock is assumed to be 20 MHz, and the desired UART configuration is:
■ 115200 baud rate
July 16, 2013
859
Texas Instruments-Production Data