TM4C1231E6PM Datasheet, PDF (78/1133 Pages) Texas Instruments – Brown-Out Reset Control (PBORCTL), offset 0x030

The Cortex-M4F Processor
Register 22: Floating-Point Status Control (FPSC)
The FPSC register provides all necessary user-level control of the floating-point system.
Floating-Point Status Control (FPSC)
Type R/W, reset -
31
30
29
28
27
26
25
24
23
22
21
N
Z
C
V
reserved AHP
DN
FZ
RMODE
Type R/W
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
RO
Reset
-
-
-
-
0
-
-
-
-
-
0
15
14
13
12
11
10
9
8
7
6
5
reserved
IDC
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
R/W
RO
RO
Reset
0
0
0
0
0
0
0
0
-
0
0
20
19
18
17
16
reserved
RO
RO
RO
RO
RO
0
0
0
0
0
4
3
2
1
0
IXC
UFC
OFC
DZC
IOC
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
Bit/Field
31
30
29
28
27
26
25
24
Name
N
Z
C
V
reserved
AHP
DN
FZ
Type
R/W
R/W
R/W
R/W
RO
R/W
R/W
R/W
Reset
-
-
-
-
0
-
-
-
Description
Negative Condition Code Flag
Floating-point comparison operations update this condition code flag.
Zero Condition Code Flag
Floating-point comparison operations update this condition code flag.
Carry Condition Code Flag
Floating-point comparison operations update this condition code flag.
Overflow Condition Code Flag
Floating-point comparison operations update this condition code flag.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Alternative Half-Precision
When set, alternative half-precision format is selected. When clear,
IEEE half-precision format is selected.
The AHP bit in the FPDSC register holds the default value for this bit.
Default NaN Mode
When set, any operation involving one or more NaNs returns the Default
NaN. When clear, NaN operands propagate through to the output of a
floating-point operation.
The DN bit in the FPDSC register holds the default value for this bit.
Flush-to-Zero Mode
When set, Flush-to-Zero mode is enabled. When clear, Flush-to-Zero
mode is disabled and the behavior of the floating-point system is fully
compliant with the IEEE 754 standard.
The FZ bit in the FPDSC register holds the default value for this bit.
78
July 16, 2013
Texas Instruments-Production Data