TMS320DM6467T_15 Datasheet, PDF (85/352 Pages) Texas Instruments – Digital Media System-on-Chip

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TMS320DM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
Table 4-2. VDD3P3V_PWDN Register Bit Descriptions (continued)
NAME
UR2DAT
UR1FC
UR1DAT
UR0MDM
UR0DF
VPIF3
VPIF2
VPIF1
VPIF0
DESCRIPTION
UART2 Data Powerdown Control.
This bit controls the URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI and
UTXD2/URCTX2/CRG1_PO/GP[40]/CRG0_PO pins.
UART1 Flow Control Powerdown Control.
This bit controls the URTS1/UIRTX1/TS0_WAITO/GP[25] and
UCTS1/USD1/TS0_EN_WAITO/GP[26] pins.
UART1 Data Powerdown Control.
This bit controls the URXD1/TS0_DIN7/GP[23] and UTXD1/URCTX1/TS0_DOUT7/GP[24] pins.
UART0 Modem Control Powerdown Control.
This bit controls the UDTR0/TS0_ENAO/GP[36], UDSR0/TS0_PSTO/GP[37],
UDCD0/TS0_WAITIN/GP[38], and URIN0/GP[8]/TS1_WAITIN pins.
UART0 Data and Flow Control Powerdown Control.
This bit controls the URXD0/TS1_DIN, UTXD0/URCTX0/TS1_PSTIN,
URTS0/UIRTX0/TS1_EN_WAITO, and UCTS0/USD0 pins.
VPIF MSB Output Powerdown Control.
This bit controls the VP_DOUT[15:8]/TS1_xx, VP_CLKIN3/TS1_CLKO, and VP_CLKO3/TS0_CLKO
pins.
VPIF LSB Output Powerdown Control.
This bit controls the VP_DOUT[7:0], VP_CLKIN2, and VP_CLKO2 pins. (VP_DOUT[7:0] are boot
configuration inputs.)
VPIF MSB Input Powerdown Control.
This bit controls the VP_DIN[15:8]/TS0_DIN[7:0] and VP_CLKIN1 pins.
VPIF LSB Input Powerdown Control.
This bit controls the VP_DIN[3:0]/TS0_DOUT[3:0], VP_DIN[7:4]/TS0_DOUT[7:4]/TS1_xx, and
VP_CLKIN0 pins.
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Device Configurations
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