TMS320DM6467T_15 Datasheet, PDF (240/352 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
www.ti.com
7.14 Video Data Conversion Engine (VDCE)
The DM6467T Video Data Conversion Engine (VDCE) supports the following features:
• Resize function on horizontal (HRSZ) and vertical (VRSZ) with ratio defined by 256/N (N is a natural
number that ranges from 256 to 2048) with 4 taps interpolation. Magnification ratio of horizontal resize
and vertical resize can be configured separately (different value can be configured).
• Anti-alias filter (combination of two kinds of low-pass filter) with horizontal 7 taps, and vertical direction.
• Chrominance signal format conversion (CCV) on both directions, one is from 4:2:2 to 4:2:0 and one is
from 4:2:0 to 4:2:2. This function also uses 4 taps interpolation. MPEG-1 specific format (half-pixel
phased from even pixel position of luminance) is also supported.
• Edge padding for preparation of MC with unrestricted motion vector (required by MPEG-4, H.264, VC-
1). All modes (progressive, interlace frame, and interlace field) are supported (macro-block level
control that is required in H.264 is not currently supported).
• VC-1 range mapping in advanced profile (in case of displaying decoded reference image or trans-
coding from VC-1 to any other format of video codec).
• 2-bit hardware menu overlay with 256 steps of blending for each color.
7.14.1 VDCE Bus Master
The VDCE includes a bus master interface that accesses the DM646x system bus to transfer data.
Table 7-58 shows the memory map for the VDCE interface.
START ADDRESS
0x0000 0000
0x1000 0000
0x1001 0000
0x1001 4000
0x1001 8000
0x1002 0000
0x1100 0000
0x4200 0000
0x4400 0000
0x4600 0000
0x4800 0000
0x4A00 0000
0x4C00 0000
0x5000 0000
0x8000 0000
0xA000 0000
0xC000 0000
Table 7-58. VDCE Master Memory Map
END ADDRESS
0x0FFF FFFF
0x1000 FFFF
0x1001 3FFF
0x1001 7FFF
0x1001 FFFF
0x10FF FFFF
0x41FF FFFF
0x43FF FFFF
0x45FF FFFF
0x47FF FFFF
0x49FF FFFF
0x4BFF FFFF
0x4FFF FFFF
0x7FFF FFFF
0x9FFF FFFF
0xBFFF FFFF
0xFFFF FFFF
SIZE
(BYTES)
256M
64K
16K
16K
32K
16256K
784M
32M
32M
32M
32M
32M
64M
768M
512M
512M
1G
VDCE ACCESS
Reserved
Reserved
ARM RAM 0 (Data)
ARM RAM 1 (Data)
ARM ROM (Data)
Reserved
EMIFA Data (CS2)
EMIFA Data (CS3)
EMIFA Data (CS4)
EMIFA Data (CS5)
Reserved
VLYNQ (Remote Data)
Reserved
DDR2 Memory Controller
Reserved
Reserved
240 Peripheral Information and Electrical Specifications
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