TMS320DM6467T_15 Datasheet, PDF (221/352 Pages) Texas Instruments – Digital Media System-on-Chip

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VIDCLKCTL.VCH3CLK
TMS320DM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
VP_CLKIN3/TS1_CLKO
VP_CLKIN2
GP[4]/STC_CLKIN
VP_CLKIN0
DEV_MXI/DEV_CLKIN
PLL
Controller 1
VP_CLKIN3
111
VP_CLKIN2
110
STC_CLKIN
101
VP_CLKIN0
100
AUXCLK
011
SYSCLK8^(A)
010
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
CRG1_VCXI
001
VPIF
Channel 3
Output Clock Source
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO
11x CRG0_VCXI
000
10x
PINMUX0.CRGMUX
VSCLKDIS.VID3
(A) For the -1G device, use an external clock source for the 54-/74.25-/108-/148.5-MHz VPIF clock.
Figure 7-37. VPIF Display Channel 3 Source Clock Selection
Copyright © 2009–2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 221
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