TM4C1236H6PM Datasheet, PDF (845/1236 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1236H6PM Microcontroller
Bit/Field
5
4
3
2:1
0
Name
TXFF
RXFE
BUSY
reserved
CTS
Type
RO
Reset
0
Description
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
0 The transmitter is not full.
1 If the FIFO is disabled (FEN is 0), the transmit holding register
is full.
If the FIFO is enabled (FEN is 1), the transmit FIFO is full.
RO
1
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
0 The receiver is not empty.
1 If the FIFO is disabled (FEN is 0), the receive holding register
is empty.
If the FIFO is enabled (FEN is 1), the receive FIFO is empty.
RO
0
UART Busy
Value Description
0 The UART is not busy.
1 The UART is busy transmitting data. This bit remains set until
the complete byte, including all stop bits, has been sent from
the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RO
0
Clear To Send
Value Description
0 The U1CTS signal is not asserted.
1 The U1CTS signal is asserted.
June 12, 2014
845
Texas Instruments-Production Data